MCIMX6Q4AVT08AC Freescale Semiconductor, MCIMX6Q4AVT08AC Datasheet - Page 7

• Manufacturer Part Number: MCIMX6Q4AVT08AC
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q4AVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Operating Supply Voltage: 1.05 V to 1.5 V
• Memory Type: L1/L2 Cache, ROM, SRAM

The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power
consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators:
Security functions are enabled and accelerated by the following hardware:
1.3
The signal names of the i.MX6 series of products have been standardized to better align the signal names
within the family and across the documentation. Some of the benefits of these changes are as follows:
This change applies only to signal names. The original ball names have been preserved to prevent the need
to change schematics, BSDL models, IBIS models, etc.
Throughout this document, the updated signal names are used except where referenced as a ball name
(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal
name changes is in the document, IMX 6 Series Signal Name Mapping (EB792). This list can be used to
map the signal names used in older documentation to the new standardized naming conventions.
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VPU—Video Processing Unit
IPUv3H—Image Processing Unit version 3H (2 IPUs)
GPU3Dv4—3D Graphics Processing Unit (OpenGL ES 2.0) version 4
GPU2Dv2—2D Graphics Processing Unit (BitBlt)
GPUVG—OpenVG 1.1 Graphics Processing Unit
ASRC—Asynchronous Sample Rate Converter
ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or
blocking the access to the system debug features.
CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM and
True and Pseudo Random Number Generator (NIST certified)
SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock
CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
The names are unique within the scope of an SoC and within the series of products
Searches will return all occurrences of the named signal
The names are consistent between i.MX 6 series products implementing the same modules
The module instance is incorporated into the signal name
Updated Signal Naming Convention
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
Introduction
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