MCIMX6S4AVM08ABR Freescale Semiconductor, MCIMX6S4AVM08ABR Datasheet - Page 74

• Manufacturer Part Number: MCIMX6S4AVM08ABR
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S4AVM08ABR

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: Parallel
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Electrical Characteristics
4.10.3
4.10.3.1 Command and Address Timing
74
1
For DDR Source sync mode,
window. The typical value of tDQSQ is 0.85ns (max) and 1ns (max) for tQHS at 200MB/s.
GPMI will sample DQ[7:0] at both rising and falling edge of an delayed DQS signal, which can
be provided by an internal DPLL. The delay value can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET(see the GPMI chapter of the i.MX
6Solo/6DualLite reference manual). Generally, the typical delay value of this register is equal
to 0x7 which means 1/4 clock cycle delay expected. But if the board delay is big enough and
cannot be ignored, the delay value should be made larger to compensate the board delay.
GPMI’s Sync Mode output timing could be controlled by module’s internal registers, say
HW_GPMI_TIMING2_CE_DELAY, HW_GPMI_TIMING_PREAMBLE_DELAY, and
HW_GPMI_TIMING2_POST_DELAY. This AC timing depends on these registers’ settings. In the above table, we
use CE_DELAY/PRE_DELAY/POST_DELAY to represent each of these settings.
NF18
NF19
NF20
NF21
NF22
NF23
NF24
NF25
NF26
NF27
ID
Samsung Toggle Mode AC Timing
Samsung Toggle Mode command and address timing is the same as ONFI
1.0 compatible Async mode AC timing. See
Mode AC Timing (ONFI 1.0 Compatible),”
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
CE# access time
CE# hold time
Command/address DQ
setup time
Command/address DQ
hold time
clock period
preamble delay
postamble delay
CLE and ALE setup time
CLE and ALE hold time
Data input to first DQS
latching transition
Parameter
Table 52. Source Synchronous Mode Timing Parameters
Figure 37
Symbol
tDQSS
tPOST
tCALS
tCALH
tCAS
tCAH
tPRE
tCH
tCE
tCK
shows the timing diagram of DQS/DQ read valid
NOTE
POST_DELAY x tCK
PRE_DELAY x tCK
CE_DELAY x tCK
0.5 x tCK
0.5 x tCK
0.5 x tCK
0.5 x tCK
0.5 x tCK
Min.
tCK
Section 4.10.1, “Asynchronous
5
for details.
T = GPMI Clock Cycle
Timing
Max.
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Freescale Semiconductor
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