MCIMX503CVK8B Freescale Semiconductor, MCIMX503CVK8B Datasheet - Page 59

• Manufacturer Part Number: MCIMX503CVK8B
• Description: Processors - Application Specialized CODEX 13MM REV 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX503CVK8B

• Core: ARM Cortex A8
• Processor Series: i.MX50
• Data Bus Width: 32 bit
• Operating Supply Voltage: 0.75 V to 1.275 V
• Memory Type: L1/L2 Cache, ROM, SRAM

1
4.7
The following sections provide information on the EIM.
4.7.1
Figure
signals may be asserted and de-asserted by an internal clock synchronized to the EIM_BCLK rising edge
according to corresponding assertion/negation control fields.
Freescale Semiconductor
GPMI’s sync mode output timing could be controlled by module’s internal register, say HW_GPMI_TIMING2_CE_DELAY,
HW_GPMI_TIMING_PREAMBLE_DELAY, HW_GPMI_TIMING2_POST_DELAY. This AC timing depends on these registers’
setting. In the above table, we use CE_DELAY/PRE_DELAY/POST_DELAY representing these settings each.
,
NF23
NF24
NF25
NF26
ID
17,
External Interface Module (EIM)
Figure
General EIM Timing
preamble delay
postamble delay
CLE and ALE setup time
CLE and ALE hold time
18, and
EIM_BCLK
EIM_ADDR
EIM_DATA
Parameter
EIM_CSx
Table 41. Samsung Toggle Mode Timing Parameters
EIM_LBA
EIM_EBx
EIM_RW
EIM_OE
i.MX50 Applications Processors for Consumer Products, Rev. 4
WE16
Table 42
WE10
WE14
WE12
WE4
WE8
WE6
Figure 17. EIM Outputs Timing Diagram
specify the timings related to the EIM module. All EIM output control
WE1
Symbol
t
t
t
t
POST
CALS
CALH
PRE
WE2
(PRE_DELAY+1)*t
POST_DELAY*t
0.5*t
0.5*t
Min.
CK
CK
...
T = GPMI Clock Cycle
WE3
CK
CK
Timing
1
(continued)
WE11
WE5
WE7
WE13
WE15
WE17
WE9
Max.
Electrical Characteristics
—
—
—
—
Unit
ns
ns
ns
ns
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