MCIMX503CVK8B Freescale Semiconductor, MCIMX503CVK8B Datasheet - Page 92
MCIMX503CVK8B
Manufacturer Part Number
MCIMX503CVK8B
Description
Processors - Application Specialized CODEX 13MM REV 1.1
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX503EVM8B.pdf
(135 pages)
Specifications of MCIMX503CVK8B
Core
ARM Cortex A8
Processor Series
i.MX50
Data Bus Width
32 bit
Operating Supply Voltage
0.75 V to 1.275 V
Memory Type
L1/L2 Cache, ROM, SRAM
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Electrical Characteristics
92
SS47
SS48
SS49
SS50
SS51
ID
Oversampling clock period
Oversampling clock high period
Oversampling clock rise time
Oversampling clock low period
Oversampling clock fall time
•
•
•
•
•
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS as shown in both the
tables and figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
Tx and Rx refer to the transmit and receive sections of the SSI.
The terms WL and BL refer to word length (WL) and bit length (BL).
For internal frame sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
Table 66. SSI Receiver Timing with Internal Clock (continued)
i.MX50 Applications Processors for Consumer Products, Rev. 4
Parameter
Oversampling Clock Operation
NOTE
15.04
Min
6.0
6.0
—
—
Freescale Semiconductor
Max
3.0
3.0
—
—
—
Unit
ns
ns
ns
ns
ns
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