IS42S16100E-7TL ISSI, Integrated Silicon Solution Inc, IS42S16100E-7TL Datasheet - Page 25

• Manufacturer Part Number: IS42S16100E-7TL
• Description: IC SDRAM 16MBIT 143MHZ 50TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16100E-7TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 16M (1M x 16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 50-TSOPII
• Organization: 1Mx16
• Density: 16Mb
• Address Bus: 12b
• Access Time (max): 6/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 50
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1071; IS42S16100E-7TL

IS42S16100E, IC42S16100E
Burst Read
The read cycle is started by executing the read command.
The address provided during read command execution is
used as the starting address. First, the data corresponding to
this address is output in synchronization with the clock signal
after the CAS latency period. Next, data corresponding to
an address generated automatically by the device is output
in synchronization with the clock signal.
The output buffers go to the LOW impedance state CAS
latency minus one cycle after the read command, and go to
the HIGH impedance state automatically after the last data
is output. However, the case where the burst length
Burst Write
The write cycle is started by executing the command.
The address provided during write command execution
is used as the starting address, and at the same time,
data for this address is input in synchronization with the
clock signal.
Next, data is input in other in synchronization with the
clock signal. During this operation, data is written to
address generated automatically by the device. This cycle
terminates automatically after a number of clock cycles
determined by the stipulated burst length. However, the
case where the burst length is a full page is an exception.
In this case the write cycle must be terminated by executing
CAS latency = 2,3, burst length = 4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
CAS latency = 3, burst length = 4
COMMAND
DQ8-DQ15
COMMAND
DQ0-DQ 7
UDQM
LDQM
CLK
CLK
DQ
READ (CA=A, BANK 0)
READ A0
D
WRITE
IN
0
DATA MASK (UPPER BYTE)
BURST LENGTH
D
IN
1
DATA MASK (LOWER BYTE)
t
QMD=2
D
D
OUT
OUT
D
IN
A0
A0
2
is a full page is an exception. In this case the output buffers
must be set to the high impedance state by executing a
burst stop command.
Note that upper byte and lower byte output data can
be masked independently under control of the signals
applied to the U/LDQM pins. The delay period (t
fixed at two, regardless of the CAS latency setting, when
this function is used.
The selected bank must be set to the active state before
executing this command.
a burst stop command. The latency for DQ pin data input
is zero, regardless of the CAS latency setting. However, a
wait period (write recovery: t
required for the device to complete the write operation.
Note that the upper byte and lower byte input data can
be masked independently under control of the signals
applied to the U/LDQM pins. The delay period (t
fixed at zero, regardless of the CAS latency setting, when
this function is used.
The selected bank must be set to the active state before
executing this command.
D
OUT
D
IN
HI-Z
A1
3
D
OUT
HI-Z
A2
D
OUT
A3
dpl
HI-Z
) after the last data input is
qmd
dmd
) is
) is
25