IS42S16100E-7TL ISSI, Integrated Silicon Solution Inc, IS42S16100E-7TL Datasheet - Page 31

• Manufacturer Part Number: IS42S16100E-7TL
• Description: IC SDRAM 16MBIT 143MHZ 50TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16100E-7TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 16M (1M x 16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 50-TSOPII
• Organization: 1Mx16
• Density: 16Mb
• Address Bus: 12b
• Access Time (max): 6/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 50
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1071; IS42S16100E-7TL

IS42S16100E, IC42S16100E
Precharge
The precharge command sets the bank selected by
pin A11 to the precharged state. This command can be
executed at a time t
command to the same bank. The selected bank goes to
the idle state at a time t
precharge command, and an active command can be
executed again for that bank.
If pin A10 is low when this command is executed, the bank
selected by pin A11 will be precharged, and if pin A10 is
HIGH, both banks will be precharged at the same time.
This input to pin A11 is ignored in the latter case.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
CAS latency = 3, burstlength = 4
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
CLK
DQ
DQ
ras
following the execution of an active
rp
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
following the execution of the
READ A0
READ A0
PRECHARGE (BANK 0)
D
OUT
A0 D
D
PRE 0
PRE 0
OUT
OUT
Read Cycle Interruption
Using the Precharge Command
A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
command to the completion of the burst output is the
clock cycle of CAS latency.
A0 D
A1 D
PRECHARGE (BANK 0)
CAS Latency
t
RQL
OUT
OUT
t
rql
rql
A1 D
A2
t
RQL
) from the execution of the precharge
OUT
HI-Z
A2
HI-Z
3
3
2
2
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