C8051F572-IMR Silicon Labs, C8051F572-IMR Datasheet - Page 102
![no-image](/images/no-image-200.jpg)
C8051F572-IMR
Manufacturer Part Number
C8051F572-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB CAN2.0 LIN 2.1 SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F556-IMR.pdf
(302 pages)
Specifications of C8051F572-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
- Current page: 102 of 302
- Download datasheet (2Mb)
C8051F55x/56x/57x
SFR Definition 12.1. SFR0CN: SFR Page Control
SFR Address = 0x84; SFR Page = 0x0F
102
7:1
Bit
Name
Reset
0
Type
Bit
SFRPGEN SFR Automatic Page Control Enable.
Unused
Name
R
7
0
Read = 0000000b; Write = Don’t Care
Upon interrupt, the C8051 Core will vector to the specified interrupt service routine
and automatically switch the SFR page to the corresponding peripheral or function’s
SFR page. This bit is used to control this autopaging function.
0: SFR Automatic Paging disabled. The C8051 core will not automatically change to
the appropriate SFR page (i.e., the SFR page that contains the SFRs for the periph-
eral/function that was the source of the interrupt).
1: SFR Automatic Paging enabled. Upon interrupt, the C8051 will switch the SFR
page to the page that contains the SFRs for the peripheral or function that is the
source of the interrupt.
R
6
0
R
5
0
Rev. 1.1
R
4
0
Function
R
3
0
R
2
0
R
1
0
SFRPGEN
R/W
0
1
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