C8051F572-IMR Silicon Labs, C8051F572-IMR Datasheet - Page 176
![no-image](/images/no-image-200.jpg)
C8051F572-IMR
Manufacturer Part Number
C8051F572-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB CAN2.0 LIN 2.1 SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F556-IMR.pdf
(302 pages)
Specifications of C8051F572-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
- Current page: 176 of 302
- Download datasheet (2Mb)
C8051F55x/56x/57x
SFR Definition 19.3. XBR2: Port I/O Crossbar Register 1
SFR Address = 0xC7; SFR Page = 0x0F
176
Name WEAKPUD
Reset
5:1
Bit
Type
7
6
0
Bit
WEAKPUD
Reserved
XBARE
LIN0E
Name
R/W
7
0
Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
Always Write to 00000b.
LIN I/O Output Enable.
0: LIN I/O unavailable at Port pin.
1: LIN_TX, LIN_RX routed to Port pins.
XBARE
R/W
6
0
R/W
5
0
Rev. 1.1
R/W
4
0
Function
Reserved
R/W
3
0
R
2
0
R/W
1
0
LIN0E
R/W
0
0
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