GT28F320C3TA110 Intel, GT28F320C3TA110 Datasheet - Page 30

• Manufacturer Part Number: GT28F320C3TA110
• Description: IC FLASH 32MBIT 110NS 47MBGA
• Manufacturer: Intel

Specifications of GT28F320C3TA110

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: Advanced + Boot Block FLASH
• Memory Size: 32M (2M x 16)
• Speed: 110ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 47-MBGA
• Other names: 820978

Intel
5.5.1
5.5.2
5.5.3
5.6
30
Figure 6. Protection Register Mapping
£
Advanced+ Boot Block Flash Memory (C3)
Reading the Protection Register
The protection register is read in the read-identifier mode. The device is switched to this mode by
issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown
in
array mode, issue the Read Array command (0xFF).
Programming the Protection Register
The protection register bits are programmed using the two-cycle Protection Program command.
The 64-bit number is programmed 16 bits at a time. First, issue the Protection Program Setup
command, 0xC0. The next write to the device will latch in address and data, and program the
specified location. The allowable addresses are shown in
page
address Protection Program commands outside the defined protection register address space should
not be attempted. Attempting to program to a previously locked protection register segment will
result in a Status Register error (Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1).
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming bit 1 of the
PR-LOCK location to 0. See
location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set
using the Protection Program command to program 0xFFFD to the PR-LOCK location. After these
bits have been programmed, no further changes can be made to the values stored in the protection
register. Protection Program commands to a locked section will result in a Status Register error
(Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1). Protection register lockout
state is not reversible.
V
The C3 device provides in-system programming and erase in the 1.65 V–3.6 V range. For fast
production programming, 12 V programming can be used. Refer to
Supply Configurations” on page
PP
Figure 6, “Protection Register
20. See
Program and Erase Voltages
Figure 18, “Protection Register Programming Flowchart” on page
0x88
0x85
0x84
0x81
0x80
Figure 6, “Protection Register Mapping” on page
15 14 13 12 11 10 9
31.
Mapping” retrieve the specified information. To return to read-
128-Bit Protection Register 0
(Intel Factory-Programmed)
PR Lock Register 0
(User-Programmable)
64-bit Segment
64-bit Segment
8
7
6
5
4
Table 6, “Device Identification Codes” on
3
2
1
0
Figure 7, “Example Power
30. Bit 0 of this
57. Attempts to
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