ATXMEGA64A3-MU Atmel, ATXMEGA64A3-MU Datasheet - Page 16
ATXMEGA64A3-MU
Manufacturer Part Number
ATXMEGA64A3-MU
Description
8-bit Microcontrollers - MCU 8/16 bit 1.6V-3.6V 64KB + 4KB
Manufacturer
Atmel
Datasheet
1.ATXMEGA64A3-MU.pdf
(134 pages)
Specifications of ATXMEGA64A3-MU
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
AVR
Data Bus Width
8 bit/16 bit
Maximum Clock Frequency
32 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Package / Case
QFN EP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
8
Data Rom Size
2 KB
Interface Type
I2C, SPI, USART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
50
Number Of Timers
7
Processor Series
ATXMega
Program Memory Type
Flash
Factory Pack Quantity
260
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.6 V
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9. Event System
9.1
9.2
8068T–AVR–12/10
Features
Overview
•
•
•
•
•
•
•
•
The Event System is a set of features for inter-peripheral communication. It enables the possibil-
ity for a change of state in one peripheral to automatically trigger actions in one or more
peripherals. What changes in a peripheral that will trigger actions in other peripherals are config-
urable by software. It is a simple, but powerful system as it allows for autonomous control of
peripherals without any use of interrupts, CPU or DMA resources.
The indication of a change in a peripheral is referred to as an event, and is usually the same as
the interrupt conditions for that peripheral. Events are passed between peripherals using a dedi-
cated routing network called the Event Routing Network.
block diagram of the Event System with the Event Routing Network and the peripherals to which
it is connected. This highly flexible system can be used for simple routing of signals, pin func-
tions or for sequencing of events.
The maximum latency is two CPU clock cycles from when an event is generated in one periph-
eral, until the actions are triggered in one or more other peripherals.
The Event System is functional in both Active and Idle modes.
Inter-peripheral communication and signalling with minimum latency
CPU and DMA independent operation
8 Event Channels allows for up to 8 signals to be routed at the same time
Events can be generated by
Events can be used by
The same event can be used by multiple peripherals for synchronized timing
Advanced Features
Functions in Active and Idle mode
– Timer/Counters (TCxn)
– Real Time Counter (RTC)
– Analog to Digital Converters (ADCx)
– Analog Comparators (ACx)
– Ports (PORTx)
– System Clock (Clk
– Software (CPU)
– Timer/Counters (TCxn)
– Analog to Digital Converters (ADCx)
– Digital to Analog Converters (DACx)
– Ports (PORTx)
– DMA Controller (DMAC)
– IR Communication Module (IRCOM)
– Manual Event Generation from software (CPU)
– Quadrature Decoding
– Digital Filtering
SYS
)
Figure 9-1 on page 17
XMEGA A3
shows a basic
16
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