ATXMEGA64A3-MU Atmel, ATXMEGA64A3-MU Datasheet - Page 57

• Manufacturer Part Number: ATXMEGA64A3-MU
• Description: 8-bit Microcontrollers - MCU 8/16 bit 1.6V-3.6V 64KB + 4KB
• Manufacturer: Atmel

Specifications of ATXMEGA64A3-MU

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: AVR
• Data Bus Width: 8 bit/16 bit
• Maximum Clock Frequency: 32 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Package / Case: QFN EP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 2 KB
• Interface Type: I2C, SPI, USART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 50
• Number Of Timers: 7
• Processor Series: ATXMega
• Program Memory Type: Flash
• Factory Pack Quantity: 260
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.6 V

32. Instruction Set Summary
8068T–AVR–12/10
Mnemonics
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
ORI
EOR
COM
NEG
SBR
CBR
INC
DEC
TST
CLR
SER
MUL
MULS
MULSU
FMUL
FMULS
FMULSU
DES
RJMP
IJMP
EIJMP
JMP
RCALL
ICALL
EICALL
Operands
Rd, Rr
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Rd
Rd,K
Rd,K
Rd
Rd
Rd
Rd
Rd
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
K
k
k
k
Description
Add without Carry
Add with Carry
Add Immediate to Word
Subtract without Carry
Subtract Immediate
Subtract with Carry
Subtract Immediate with Carry
Subtract Immediate from Word
Logical AND
Logical AND with Immediate
Logical OR
Logical OR with Immediate
Exclusive OR
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Multiply Unsigned
Multiply Signed
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Data Encryption
Relative Jump
Indirect Jump to (Z)
Extended Indirect Jump to (Z)
Jump
Relative Call Subroutine
Indirect Call to (Z)
Extended Indirect Call to (Z)
Arithmetic and Logic Instructions
Branch Instructions
else if (H = 1) then R15:R0
if (H = 0) then R15:R0
Rd + 1:Rd
PC(21:16)
PC(21:16)
PC(21:16)
PC(21:16)
PC(15:0)
PC(15:0)
PC(15:0)
PC(15:0)
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
Operation
PC
PC
PC
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Rd + Rr
Rd + Rr + C
Rd + 1:Rd + K
Rd - Rr
Rd - K
Rd - Rr - C
Rd - K - C
Rd + 1:Rd - K
Rd • Rr
Rd • K
Rd v Rr
Rd v K
Rd ⊕ Rr
$FF - Rd
$00 - Rd
Rd v K
Rd • ($FFh - K)
Rd + 1
Rd - 1
Rd • Rd
Rd ⊕ Rd
$FF
Rd x Rr (UU)
Rd x Rr (SS)
Rd x Rr (SU)
Rd x Rr<<1 (UU)
Rd x Rr<<1 (SS)
Rd x Rr<<1 (SU)
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
PC + k + 1
Z,
0
Z,
EIND
k
PC + k + 1
Z,
0
Z,
EIND
XMEGA A3
Flags
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,C,N,V,S
Z,C,N,V,S,H
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
None
Z,C
Z,C
Z,C
Z,C
Z,C
Z,C
None
None
None
None
None
None
None
#Clocks
2 / 3
2 / 3
1/2
3
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
3
(1)
(1)
(1)
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