C8051F047R Silicon Labs, C8051F047R Datasheet - Page 306
![no-image](/images/no-image-200.jpg)
C8051F047R
Manufacturer Part Number
C8051F047R
Description
8-bit Microcontrollers - MCU 25 MIPS 32KB 10ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F044R.pdf
(328 pages)
Specifications of C8051F047R
Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
32 KB
Data Ram Size
4.25 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
TQFP-64
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
13
Data Rom Size
64 KB
Interface Type
CAN, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
32
Number Of Timers
16 bit
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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C8051F040/1/2/3/4/5/6/7
24.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 24.1. Note that in ‘External oscillator
source divided by 8’ mode, the external oscillator source is synchronized with the system clock,
and must have a frequency less than or equal to the system clock.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 inter-
rupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the
CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle
mode.
304
Notes:
CPS2
1. The minimum high or low time for the ECI input signal is at least 2 system clock cycles.
2. External oscillator source divided by 8 is synchronized with the system clock.
0
0
0
0
1
1
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
CPS1
0
0
1
1
0
0
C
D
L
I
W
D
T
E
PCA0MD
W
D
C
K
L
C
P
S
2
000
001
010
011
100
101
Figure 24.2. PCA Counter/Timer Block Diagram
C
P
S
1
CPS0
C
P
S
0
E
C
F
0
1
0
1
0
1
Table 24.1. PCA Timebase Input Options
IDLE
C
F
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI
System clock
External clock divided by 8
C
R
PCA0CN
C
C
F
5
C
C
F
4
C
C
F
3
C
C
F
2
C
C
F
1
C
C
F
0
Rev. 1.5
0
1
PCA0L
read
Snapshot
Register
PCA0H
2
Timebase
1
(max rate = system clock divided by 4)
PCA0L
To SFR Bus
To PCA Modules
Overflow
CF
To PCA Interrupt System
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