C8051F047R Silicon Labs, C8051F047R Datasheet - Page 35
![no-image](/images/no-image-200.jpg)
C8051F047R
Manufacturer Part Number
C8051F047R
Description
8-bit Microcontrollers - MCU 25 MIPS 32KB 10ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F044R.pdf
(328 pages)
Specifications of C8051F047R
Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
32 KB
Data Ram Size
4.25 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
TQFP-64
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
13
Data Rom Size
64 KB
Interface Type
CAN, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
32
Number Of Timers
16 bit
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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2.
Table 2.1. Absolute Maximum Ratings*
Ambient temperature under bias
Storage Temperature
Voltage on any Pin (except V
pins) with respect to DGND
Voltage on any Port I/O Pin, /RST, and JTAG pins with
respect to DGND
Voltage on V
Maximum Total current through V
and AGND
Maximum output current sunk by any Port pin
Maximum output current sunk by any other I/O pin
Maximum output current sourced by any Port pin
Maximum output current sourced by any other I/O pin
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Absolute Maximum Ratings
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Due to special I/O design requirements of the High Voltage Difference Amplifier, undue electrical over-voltage
stress (i.e., ESD) experienced by these pads may result in impedance degradation of these inputs (HVAIN+
and HVAIN–). For this reason, care should be taken to ensure proper handling and use as typically required to
prevent ESD damage to electrostatically sensitive CMOS devices (e.g., static-free workstations, use of
grounding straps, over-voltage protection in end-applications, etc.)
DD
with respect to DGND
Parameter
DD
, Port I/O, and JTAG
DD
, AV+, DGND,
Rev. 1.5
C8051F040/1/2/3/4/5/6/7
Conditions
–0.3
–0.3
–0.3
Min
–55
–65
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
V
Max
125
150
800
100
100
DD
0.3
5.8
4.2
50
50
+
Units
mA
mA
mA
mA
mA
°C
°C
V
V
V
35
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