C8051F047R Silicon Labs, C8051F047R Datasheet - Page 324

• Manufacturer Part Number: C8051F047R
• Description: 8-bit Microcontrollers - MCU 25 MIPS 32KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F047R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 4.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 13
• Data Rom Size: 64 KB
• Interface Type: CAN, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

C8051F040/1/2/3/4/5/6/7
322
This register determines how the Flash interface logic will respond to reads and writes to the 
Bit 7:
Bits6-4:
Bits3-0:
SFLE
Bit7
JTAG Register Definition 25.3. FLASHCON: JTAG Flash Control Register
FLASHDAT Register. 
SFLE: Scratchpad Flash Memory Access Enable
When this bit is set, Flash reads and writes from user software are directed to the 128-byte
scratchpad Flash sector. When accessing the scratchpad, Flash accesses out of the
address range 0x00-0x7F should not be attempted. Reads/Writes outside of this range will
yield undefined results.
0: Flash access is directed to the Program/Data Flash sector.
1: Flash access is directed to the 128-byte scratchpad sector.
WRMD2-0: Write Mode Select Bits.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASH-
DAT Register per the following values:
000:
001:
010:
(All other values for WRMD2-0 are reserved.)
RDMD3-0: Read Mode Select Bits.
The Read Mode Select Bits control how the interface logic responds to reads to the FLASH-
DAT Register per the following values:
0000:
0001:
0010:
(All other values for RDMD3-0 are reserved.)
WRMD2
Bit6
A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise
ignored.
A FLASHDAT write initiates a write of FLASHDAT into the memory address by the
FLASHADR register. FLASHADR is incremented by one when complete.
A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page
containing the address in FLASHADR. The data written must be 0xA5 for the erase
to occur. FLASHADR is not affected. If FLASHADR targets the Read Lock Byte or
the Write/Erase Lock Byte, the entire user space will be erased (i.e. entire Flash
memory except for the Reserved area (See
page
A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise
ignored.
A FLASHDAT read initiates a read of the byte addressed by the FLASHADR regis-
ter if no operation is currently active. This mode is used for block reads.
A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no
operation is active and any data from a previous read has already been read from
FLASHDAT. This mode allows single bytes to be read (or the last byte of a block)
without initiating an extra read.
WRMD1
179).
Bit5
WRMD0
Bit4
RDMD3
Rev. 1.5
Bit3
RDMD2
Bit2
Section “15. Flash Memory” on
RDMD1
Bit1
RDMD0
Bit0
00000000
Reset Value