C8051F131R Silicon Labs, C8051F131R Datasheet - Page 241

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

18.1.6. External Memory Interface Pin Assignments
If the External Memory Interface (EMIF) is enabled on the Low ports (Ports 0 through 3), EMIFLE (XBR2.5)
should be set to a logic 1 so that the Crossbar will not assign peripherals to P0.7 (/WR), P0.6 (/RD), and if
the External Memory Interface is in Multiplexed mode, P0.5 (ALE). Figure 18.4 shows an example Cross-
bar Decode Table with EMIFLE=1 and the EMIF in Multiplexed mode. Figure 18.5 shows an example
Crossbar Decode Table with EMIFLE=1 and the EMIF in Non-multiplexed mode.
If the External Memory Interface is enabled on the Low ports and an off-chip MOVX operation occurs, the
External Memory Interface will control the output states of the affected Port pins during the execution
phase of the MOVX instruction, regardless of the settings of the Crossbar registers or the Port Data regis-
ters. The output configuration of the Port pins is not affected by the EMIF operation, except that Read
operations will explicitly disable the output drivers on the Data Bus. See
ory Interface and On-Chip XRAM” on page 219
face.
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
TX1
RX1
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
CP0
CP1
T0
/INT0
T1
/INT1
T2
T2EX
T4
T4EX
/SYSCLK
CNVSTR0
CNVSTR2
Figure 18.4. Priority Crossbar Decode Table (EMIFLE = 1; EMIF in Multiplexed
PIN I/O 0
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1
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2
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3
P0
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4
5
6
7
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0
AIN2 Inputs/Non-muxed Addr H
● ● ● ● ● ● ●
1
NSS is not assigned to a port pin when the SPI is placed in 3-wire mode
● ● ● ● ● ●
2
3
P1
Mode; P1MDIN = 0xFF)
4
5
6
7
Muxed Addr H/Non-muxed Addr L
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● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
0
Rev. 1.4
for more information about the External Memory Inter-
1
2
C8051F120/1/2/3/4/5/6/7
3
P2
4
5
6
7
0
Muxed Data/Non-muxed Data
C8051F130/1/2/3
Section “17. External Data Mem-
1
2
3
P3
4
5
6
7
Crossbar Register Bits
UART0EN:
UART1EN:
CNVSTE0: XBR2.0
CNVSTE2: XBR2.5
SMB0EN:
PCA0ME:
SYSCKE: XBR1.7
SPI0EN:
T2EXE: XBR1.6
T4EXE: XBR2.4
ECI0E: XBR0.6
INT0E: XBR1.2
INT1E: XBR1.4
CP0E: XBR0.7
CP1E: XBR1.0
T0E: XBR1.1
T1E: XBR1.3
T2E: XBR1.5
T4E: XBR2.3
XBR0.2
XBR0.1
XBR0.0
XBR2.2
XBR0.[5:3]
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