C8051F131R Silicon Labs, C8051F131R Datasheet - Page 41

• Manufacturer Part Number: C8051F131R
• Description: 8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F131R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 9
• Data Rom Size: 64 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

4.
MONEN
DGND
XTAL1
XTAL2
AGND
Pinout and Package Definitions
Name
TMS
TDO
TCK
RST
V
AV+
TDI
DD
64, 90
63, 89
11, 14
10, 13
‘F120
‘F122
‘F124
‘F126
37,
38,
26
27
28
1
2
3
4
5
Pin Numbers
41, 57
40, 56
‘F121
‘F123
‘F125
‘F127
24,
25,
58
59
60
61
62
17
18
19
6
5
64, 90
63, 89
10, 13
11, 14
‘F130
‘F132
37,
38,
26
27
28
1
2
3
4
5
Table 4.1. Pin Definitions
41, 57
40, 56
‘F131
‘F133
24,
25,
58
59
60
61
62
17
18
19
6
5
Rev. 1.4
D Out JTAG Test Data Output with internal pullup. Data
A Out Crystal Output. This pin is the excitation driver
D I/O Device Reset. Open-drain output of internal V
Type
D In JTAG Test Mode Select with internal pullup.
D In JTAG Test Clock with internal pullup.
D In JTAG Test Data Input with internal pullup. TDI is
A In Crystal Input. This pin is the return for the inter-
D In V
C8051F120/1/2/3/4/5/6/7
Digital Supply Voltage. Must be tied to +2.7 to
+3.6 V.
Digital Ground. Must be tied to Ground.
Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
Analog Ground. Must be tied to Ground.
latched on the rising edge of TCK.
is shifted out on TDO on the falling edge of TCK.
TDO output is a tri-state driver.
monitor. Is driven low when V
MONEN is high. An external source can initiate
a system reset by driving this pin low.
nal oscillator circuit for a crystal or ceramic reso-
nator. For a precision internal clock, connect a
crystal or ceramic resonator from XTAL1 to
XTAL2. If overdriven by an external CMOS
clock, this becomes the system clock.
for a crystal or ceramic resonator.
enables the internal V
system reset when V
low, the internal V
This pin must be tied high or low.
DD
Monitor Enable. When tied high, this pin
C8051F130/1/2/3
Description
DD
DD
monitor is disabled.
DD
is < V
monitor, which forces a
DD
RST
is < V
. When tied
RST
and
DD
41