C8051F131R Silicon Labs, C8051F131R Datasheet - Page 310
![no-image](/images/no-image-200.jpg)
C8051F131R
Manufacturer Part Number
C8051F131R
Description
8-bit Microcontrollers - MCU 128kB 100MIPS 8448B RAM
Manufacturer
Silicon Labs
Datasheet
1.C8051F133R.pdf
(350 pages)
Specifications of C8051F131R
Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
100 MHz
Program Memory Size
128 KB
Data Ram Size
8.25 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
TQFP-64
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
9
Data Rom Size
64 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
32
Number Of Timers
16 bit
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to
“18.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 238
and configuring external I/O pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When
T0M is set, Timer 0 is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source
selected by the Clock Scale bits in CKCON (see SFR Definition 23.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is logic-level 1. Setting GATE0 to ‘1’ allows the timer to be controlled by the external input signal /
INT0 (see
surements.
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1.
310
TR0
X = Don't Care
0
1
1
1
/INT0
T0
Section “11.3.5. Interrupt Register Descriptions” on page 157
Crossbar
GATE0
X
0
1
1
Pre-scaled Clock
SYSCLK
GATE0
/INT0
Figure 23.1. T0 Mode 0 Block Diagram
X
X
0
1
TR0
0
1
Counter/Timer
Disabled
Disabled
Enabled
Enabled
CKCON
M
T
1
0
1
M
T
0
S
C
A
1
Rev. 1.4
S
C
A
0
G
A
E
T
1
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
TL0
(8 bits)
TH0
), facilitating pulse width mea-
for information on selecting
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
Interrupt
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