ISPPAC-POWR1208-01T44E Lattice, ISPPAC-POWR1208-01T44E Datasheet - Page 20

• Manufacturer Part Number: ISPPAC-POWR1208-01T44E
• Description: Supervisory Circuits PROGRAMMABLE PWR SUPPLY CONTR
• Manufacturer: Lattice

Specifications of ISPPAC-POWR1208-01T44E

• Number Of Voltages Monitored: 12
• Monitored Voltage: Adjustable
• Undervoltage Threshold: 1.03 V
• Overvoltage Threshold: 5.72 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 800
• Supply Current (typ): 15000 uA
• Supply Voltage - Min: 2.25 V

Lattice Semiconductor
ispPAC-POWR1208 Data Sheet
IEEE Standard 1149.1 Interface
Communication with the ispPAC-POWR1208 is facilitated via an IEEE 1149.1 test access port (TAP). It is used by
the ispPAC-POWR1208 as a serial programming interface, and not for boundary scan test purposes. There are no
boundary scan logic registers in the ispPAC-POWR1208 architecture. This does not prevent the ispPAC-
POWR1208 from functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 compli-
ant devices. Since the ispPAC-POWR1208 is used to powerup other devices, it should be programmed in a sepa-
rate chain from PLDs, FPGAs or other JTAG devices.
A brief description of the ispPAC-POWR1208 serial interface follows. For complete details of the reference specifi-
cation, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990
(which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the isp-
PAC-POWR1208. The TAP controller is a state machine driven with mode and clock inputs. Under the correct pro-
tocol, instructions are shifted into an instruction register, which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing various registers, shifting data in,
and then executing the respective program instruction. The programming instructions transfer the data into internal
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CMOS memory. It is these non-volatile memory cells that determine the configuration of the ispPAC-POWR1208.
By cycling the TAP controller through the necessary states, data can also be shifted out of the various registers to
verify the current ispPAC-POWR1208 configuration. Instructions exist to access all data registers and perform
internal control operations.
For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification.
Other registers are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional
user data registers that are defined by the manufacturer. The two required registers are the bypass and boundary-
scan registers. For ispPAC-POWR1208, the bypass register is a 1-bit shift register that provides a short path
through the device when boundary testing or other operations are not being performed. The ispPAC-POWR1208,
as mentioned earlier has no boundary-scan logic and therefore no boundary scan register. All instructions relating
to boundary scan operations place the ispPAC-POWR1208 in the BYPASS mode to maintain compliance with the
specification.
The optional identification (IDCODE) register described in IEEE 1149.1 is also included in the ispPAC-POWR1208.
Six additional user data registers are included in the TAP of the ispPAC-POWR1208 as shown in Figure 10. Most of
these additional registers are used to program and verify the analog configuration (CFG) and PLD bits. A status
register is also provided to read the status of the twelve analog comparators.
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