ISPPAC-POWR1208-01T44E Lattice, ISPPAC-POWR1208-01T44E Datasheet - Page 21

• Manufacturer Part Number: ISPPAC-POWR1208-01T44E
• Description: Supervisory Circuits PROGRAMMABLE PWR SUPPLY CONTR
• Manufacturer: Lattice

Specifications of ISPPAC-POWR1208-01T44E

• Number Of Voltages Monitored: 12
• Monitored Voltage: Adjustable
• Undervoltage Threshold: 1.03 V
• Overvoltage Threshold: 5.72 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 800
• Supply Current (typ): 15000 uA
• Supply Voltage - Min: 2.25 V

Lattice Semiconductor
Figure 10. TAP Registers
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller. In a given state, the controller responds according to the level on the TMS input as shown
in Figure 11. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becom-
ing valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-Test/
Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register, and Pause-Instruction-Register. But
there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state
and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction
scan is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or
instruction scan is performed. The states of the Data and Instruction Register blocks are identical to each other dif-
fering only in their entry points. When either block is entered, the first action is a capture operation. For the Data
Registers, the Capture-DR state is very simple; it captures (parallel loads) data onto the selected serial data path
(previously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always
load the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior
to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a “blind” interrogation of any device in
a compliant IEEE 1149.1 serial chain.
TDI
ANALOG COMPARATOR ARRAY (12 bits)
PLD ADDRESS REGISTER (75 bits)
CFG ADDRESS REGISTER (4 bits)
INSTRUCTION REGISTER (6 bits)
TEST ACCESS PORT
PLD DATA REGISTER (81 bits)
TCK
STATUS REGISTER (12 bits)
IDCODE REGISTER (32 bits)
BYPASS REGISTER (1 bit)
UES REGISTER (16 bits)
CFG REGISTER (41 bits)
(TAP) LOGIC
TMS
21
OUTPUT
LATCH
TDO
ispPAC-POWR1208 Data Sheet
E
E
CONFIGURATION
2
2
NON-VOLATILE
NON-VOLATILE
AND / ARCH
(6075 bits)
MEMORY
MEMORY
ANALOG
(164 bits)
PLD