ISPPAC-POWR1208-01T44E Lattice, ISPPAC-POWR1208-01T44E Datasheet - Page 28

• Manufacturer Part Number: ISPPAC-POWR1208-01T44E
• Description: Supervisory Circuits PROGRAMMABLE PWR SUPPLY CONTR
• Manufacturer: Lattice

Specifications of ISPPAC-POWR1208-01T44E

• Number Of Voltages Monitored: 12
• Monitored Voltage: Adjustable
• Undervoltage Threshold: 1.03 V
• Overvoltage Threshold: 5.72 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 800
• Supply Current (typ): 15000 uA
• Supply Voltage - Min: 2.25 V

Lattice Semiconductor
ispPAC-POWR1208 Data Sheet
Software-Based Design Environment
Design Entry Software
All functions within the ispPAC-POWR1208 are controlled through a Windows-based software development tool
called PAC-Designer. PAC-Designer is an easy-to-use graphical user interface (Figure 17) that allows the user to
set up the ispPAC-POWR1208 to perform given functions, such as timed sequences for power supply and monitor
trip points for the voltage monitor inputs. The software tool gives the user control over how the device drives the
outputs and the functional configurations for all I/O pins. User-friendly dialog boxes are provided to set and edit all
of the analog features of the ispPAC-POWR1208. An extension to the schematic screen is the LogiBuilder design
environment (Figure 18) that is used to enter and edit control sequences. Again, user-friendly dialog boxes are pro-
vided in this window to help the designer to quickly implement sequences that take advantage of the powerful built-
in PLD. Once the configurations are chosen and the sequence has been described by the utilities, the device is
2
ready to program. A standard JTAG interface is used to program the E
CMOS memory. PAC-Designer software
supports downloading the device through the PC’s parallel port. The ispPAC-POWR1208 can be reprogrammed
®
using the software and ispDOWNLOAD
Cable assembly, to adjust for variations in supply timing, sequencing or
scaling of voltage monitor inputs.
Figure 17. PAC-Designer Schematic Screen
The user interface (Figure 17) provides access to various internal function blocks within the ispPAC-POWR1208
device.
Analog Inputs: Accesses the programmable threshold trip-points for the comparators and pin naming conven-
tions.
Digital Inputs: Digital input naming configurations and digital inputs feed into the internal PLD for the sequence
controller.
Sequence Controller: Incorporates a PLD architecture for designing the state machine to control the order and
functions associated with the user-defined power-up sequence/monitor and control.
28