AT25DF321A-SH-B Atmel, AT25DF321A-SH-B Datasheet - Page 29

• Manufacturer Part Number: AT25DF321A-SH-B
• Description: IC FLASH 32MBIT 100MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25DF321A-SH-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 32M (16384 pages x 256 Bytes)
• Speed: 100MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Memory Configuration: 16384 Pages X 256 Bytes
• Interface Type: Serial, SPI
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3686D–DFLASH–12/09
10.5
Figure 10-5.
SCK
SO
CS
SI
If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte user
programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed again.
The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the contents of
the buffer will be altered from its previous state when this command is issued.
Figure 10-4. Program OTP Security Register
Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum
clock frequency specified by f
77h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to
specify the starting address location of the first byte to read within the OTP Security Register. Following the three address
bytes, two dummy bytes must be clocked into the device before data can be output.
After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP Security
Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security Register has been read, the
device will continue reading back at the beginning of the register (000000h). No delays will be incurred when wrapping
around from the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can
be deasserted at any time and does not require that a full byte of data be read.
SCK
SO
CS
SI
Read OTP Security Register
MSB
HIGH-IMPEDANCE
0
0
1
1
1
2
OPCODE
1
HIGH-IMPEDANCE
MSB
3
1
0
0
4
0
1
1
5
0
2
OPCODE
1
6
1
3
1
7
1
MAX
MSB
4
A
8
0
5
. To read the OTP Security Register, the CS pin must first be asserted and the opcode of
A
9
ADDRESS BITS A23-A0
1
6
A
10 11
1
7
A
MSB
A
ADDRESS BITS A23-A0
8
A
12
A
9
A
A
A
29 30
A
29 30
A
A
A
31 32
A
31 32
MSB
X
MSB
D
X
33
D
33
DATA IN BYTE 1
X
34
D
34
X
DON'T CARE
35
D
35
X
36
D
36
X
D
37 38
D
X
D
39
X
X
MSB
MSB
D
D
D
D
DATA IN BYTE n
DATA BYTE 1
Atmel AT25DF321A
D
D
D
D
D
D
D
D
D
D
D
D
MSB
D
D
29