EVAL-ADXL312Z Analog Devices, EVAL-ADXL312Z Datasheet - Page 13

• Manufacturer Part Number: EVAL-ADXL312Z
• Description: Daughter Cards & OEM Boards EB Digital Output Three-Axis Accel
• Manufacturer: Analog Devices
• Series: ADXL312r

Specifications of EVAL-ADXL312Z

• Rohs: yes
• Product: Evaluation Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2 V to 3.6 V
• Factory Pack Quantity: 1
• For Use With: ADXL312

Table 8. SPI Digital Input/Output
Parameter
Digital Input
Digital Output
Pin Capacitance
1
Table 9. SPI Timing (T
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
SCLK
SCLK
DELAY
QUIET
DIS
CS,DIS
S
M
SETUP
HOLD
SDO
R
F
Limits based on characterization results, not production tested.
The CS , SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
Limits based on characterization results, characterized with f
The timing values are measured corresponding to the input thresholds (V
Output rise and fall times measured with capacitive load of 150 pF.
4
4
Low Level Input Voltage (V
High Level Input Voltage (V
Low Level Input Current (I
High Level Input Current (I
Low Level Output Voltage (V
High Level Output Voltage (V
Low Level Output Current (I
High Level Output Current (I
Min
200
5
5
150
0.3 × t
0.3 × t
5
5
SCLK
SCLK
Limit
A
= 25°C, V
IL
2, 3
IH
IL
)
IH
)
)
OL
OH
OL
)
Max
5
10
40
20
20
OH
)
)
)
)
S
= V
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DD I/O
= 3.3 V)
Description
SPI clock frequency.
1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40.
CS falling edge to SCLK falling edge .
SCLK rising edge to CS rising edge.
CS rising edge to SDO disabled.
CS deassertion between SPI communications.
SCLK low pulse width (space).
SCLK high pulse width (mark).
SDI valid before SCLK rising edge.
SDI valid after SCLK rising edge.
SCLK falling edge to SDO/SDIO output transition.
SDO/SDIO output high to output low transition.
SDO/SDIO output low to output high transition.
SCLK
= 5 MHz and bus load capacitance of 100 pF; not production tested.
Test Conditions
V
V
I
I
V
V
f
1
OL
OH
IN
IN
IN
OL
OH
= 1 MHz, V
= 10 mA
= −4 mA
= V
= 0 V
= V
= V
Rev. 0 | Page 13 of 32
DD I/O
OL, max
OH, min
IL
and V
IN
IH
) given in Table 8.
= 2.5 V
Min
0.7 × V
0.8 × V
−0.1
10
DD I/O
DD I/O
Limit
Max
1
0.3 × V
0.2 × V
0.1
−4
8
DD I/O
DD I/O
ADXL312
Unit
V
V
μA
μA
V
V
mA
mA
pF