EVAL-ADXL312Z Analog Devices, EVAL-ADXL312Z Datasheet - Page 22

• Manufacturer Part Number: EVAL-ADXL312Z
• Description: Daughter Cards & OEM Boards EB Digital Output Three-Axis Accel
• Manufacturer: Analog Devices
• Series: ADXL312r

Specifications of EVAL-ADXL312Z

• Rohs: yes
• Product: Evaluation Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2 V to 3.6 V
• Factory Pack Quantity: 1
• For Use With: ADXL312

ADXL312
the inactivity and activity functions are concurrent. Additional
information can be found in the Link Mode section.
When clearing the link bit, it is recommended that the part be
placed into standby mode and then set back to measurement
mode with a subsequent write. This is done to ensure that the
device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the link bit is cleared
may have additional noise, especially if the device was asleep
when the bit was cleared.
AUTO_SLEEP Bit
If the link bit is set, a setting of 1 in the AUTO_SLEEP bit sets
the ADXL312 to switch to sleep mode when inactivity is detected
(that is, when acceleration has been below the THRESH_INACT
value for at least the time indicated by TIME_INACT). A setting
of 0 disables automatic switching to sleep mode. See the description
of the sleep bit in this section for more information.
When clearing the AUTO_SLEEP bit, it is recommended that the
part be placed into standby mode and then set back to measure-
ment mode with a subsequent write. This is done to ensure that
the device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the AUTO_SLEEP
bit is cleared may have additional noise, especially if the device
was asleep when the bit was cleared.
Measure Bit
A setting of 0 in the measure bit places the part into standby mode,
and a setting of 1 places the part into measurement mode. The
ADXL312 powers up in standby mode with minimum power
consumption.
Sleep Bit
A setting of 0 in the sleep bit puts the part into the normal mode
of operation, and a setting of 1 places the part into sleep mode.
Sleep mode suppresses DATA_READY (see Register 0x2E, Register
0x2F, and Register 0x30), stops transmission of data to FIFO, and
switches the sampling rate to one specified by the wake-up bits.
In sleep mode, only the activity function can be used.
When clearing the sleep bit, it is recommended that the part be
placed into standby mode and then set back to measurement
mode with a subsequent write. This is done to ensure that the
device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the sleep bit is
cleared may have additional noise, especially if the device was
asleep when the bit was cleared.
Rev. 0 | Page 22 of 32
Wake-Up Bits
These bits control the frequency of readings in sleep mode as
described in Table 19.
Table 19. Frequency of Readings in Sleep Mode
D1
0
0
1
1
Register 0x2E—INT_ENABLE (Read/Write)
D7
DATA_READY
D3
Inactivity
Setting bits in this register to a value of 1 enables their respective
functions to generate interrupts, whereas a value of 0 prevents
the functions from generating interrupts. The DATA_READY,
watermark, and overrun bits enable only the interrupt output;
the functions are always enabled. It is recommended that interrupts
be configured before enabling their outputs.
Register 0x2F—INT_MAP (Read/Write)
D7
DATA_READY
D3
Inactivity
Any bits set to 0 in this register send their respective interrupts to
the INT1 pin, whereas bits set to 1 send their respective interrupts
to the INT2 pin. All selected interrupts for a given pin are OR’ e d.
Register 0x30—INT_SOURCE (Read Only)
D7
DATA_READY
D3
Inactivity
Bits set to 1 in this register indicate that their respective functions
have triggered an event, whereas a value of 0 indicates that the
corresponding event has not occurred. The DATA_READY,
watermark, and overrun bits are always set if the corresponding
events occur, regardless of the INT_ENABLE register settings,
and are cleared by reading data from the DATAX, DATAY, and
DATAZ registers. The DATA_READY and watermark bits may
require multiple reads, as indicated in the FIFO mode descriptions
in the FIFO section. Other bits, and the corresponding interrupts,
are cleared by reading the INT_SOURCE register.
Setting
D0
0
1
0
1
D6
N/A
D2
N/A
D6
N/A
D2
N/A
D6
N/A
D2
N/A
Frequency (Hz)
8
4
2
1
D5
N/A
D1
Watermark
D5
N/A
D1
Watermark
D5
N/A
D1
Watermark
D4
Activity
D0
Overrun
D4
Activity
D0
Overrun
D4
Activity
D0
Overrun