EVAL-ADXL312Z Analog Devices, EVAL-ADXL312Z Datasheet - Page 16

• Manufacturer Part Number: EVAL-ADXL312Z
• Description: Daughter Cards & OEM Boards EB Digital Output Three-Axis Accel
• Manufacturer: Analog Devices
• Series: ADXL312r

Specifications of EVAL-ADXL312Z

• Rohs: yes
• Product: Evaluation Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2 V to 3.6 V
• Factory Pack Quantity: 1
• For Use With: ADXL312

ADXL312
Table 11. I
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
4
5
6
7
SCL
1
2
3
4
5
6
7
8
9
10
11
undefined region of the falling edge of SCL.
Limits based on characterization results, with f
All values referred to the V
t
A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to V
The maximum t
The maximum value for t
t
C
b
3, 4, 5, 6
6
6(max)
b
SDA
SCL
is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge.
is the total capacitance of one bus line in picofarads.
= t
3
− t
2
10
C Timing (T
− t
6
value must be met only if the device does not stretch the low period (t
5(min)
t
9
.
CONDITION
6
is a function of the clock low time (t
IH
START
and the V
A
Min
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
0
20 + 0.1 C
t
4
= 25°C, V
IL
t
levels given in Table 10.
3
b
Limit
7
S
= V
SCL
1, 2
Max
400
0.9
300
250
300
400
= 400 kHz and a 3 mA sink current; not production tested.
DD I/O
t
10
t
6
= 3.3 V)
3
), the clock rise time (t
Unit
kHz
μs
μs
μs
μs
ns
μs
μs
μs
μs
ns
ns
ns
ns
ns
pF
Figure 28. I
t
2
Rev. 0 | Page 16 of 32
2
C Timing Diagram
t
11
Description
SCL clock frequency
SCL cycle time
t
t
t
t
t
t
t
t
t
t
t
t
t
Capacitive load for each bus line
HIGH
LOW
HD, STA
SU, DAT
HD, DAT
SU, STA
SU, STO
BUF
R
R
F
F
F
, rise time of both SCL and SDA when receiving
, rise time of both SCL and SDA when receiving or transmitting
, fall time of SDA when receiving
, fall time of both SCL and SDA when transmitting
, fall time of both SCL and SDA when transmitting or receiving
t
10
, bus-free time between a stop condition and a start condition
5
, SCL low time
, SCL high time
), and the minimum data setup time (t
, setup time for repeated start
3
, start/repeated start condition hold time
, data setup time
, stop condition setup time
, data hold time
) of the SCL signal.
CONDITION
REPEATED
START
t
7
t
4
IH(min)
5(min)
of the SCL signal) to bridge the
). This value is calculated as
t
1
CONDITION
STOP
t
8