IS42S32800D-6TL ISSI, Integrated Silicon Solution Inc, IS42S32800D-6TL Datasheet - Page 15

• Manufacturer Part Number: IS42S32800D-6TL
• Description: IC SDRAM 256MBIT 166MHZ 86TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32800D-6TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TSOPII
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 13b
• Access Time (max): 6.5/5.4ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 166 MHz
• Access Time: 6.5 ns, 5.4 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S32800D
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
11/21/07
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Mode Register Set command
(RAS#=”L”,CAS#=”L”,WE#=”L”,BS0,1 and A11-A0 =Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM.The Mode Register Set
command programs the values of CAS#latency,Addressing Mode and Burst Length in the Mode register to make
SDRAM useful for a variety of different applications.The default values of the Mode Register after power-up are
undefined;therefore this command must be issued at the power-up sequence.The state of pins BS0,1 and
A11~A0 in the same cycle is the data written to the mode register.One clock cycle is required to complete the write
in the mode register (refer to the following figure).The contents of the mode register can be changed using the
same command and the clock cycle requirements during operation as long as all banks are in the idle state.
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