IS61NVP51236-200TQLI ISSI, Integrated Silicon Solution Inc, IS61NVP51236-200TQLI Datasheet - Page 9

• Manufacturer Part Number: IS61NVP51236-200TQLI
• Description: IC SRAM 18MBIT 200MHZ 100TQFP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61NVP51236-200TQLI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Density: 18Mb
• Access Time (max): 3.1ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 2.5V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 475mA
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418
ASYNCHRONOUS TRUTH TABLE
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE
Notes
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. M
01/06/2011
Operation
Sleep Mode
Read
Write
Deselected
Operation
READ
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ABORT/NOP
Operation
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
bus contention will occur.
:
(x18)
(x36)
ZZ
H
L
L
L
L
WE
WE
H
H
L
L
L
L
L
L
L
L
L
L
(1)
BWa
X
H
H
H
H
L
L
OE
X
H
X
X
L
BWa
X
H
H
L
L
BWb
H
H
H
H
X
L
L
BWc
I/O STATUS
Din, High-Z
X
H
H
H
H
L
L
High-Z
High-Z
High-Z
BWb
DQ
X
H
H
L
L
BWd
X
H
H
H
H
L
L
9