M25P80-VMN6TP NUMONYX, M25P80-VMN6TP Datasheet - Page 10
![IC FLASH 8MBIT 75MHZ 8SOIC](/photos/7/28/72830/m25p80-vmn6tp_sml.jpg)
M25P80-VMN6TP
Manufacturer Part Number
M25P80-VMN6TP
Description
IC FLASH 8MBIT 75MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P80-VMP6G.pdf
(57 pages)
Specifications of M25P80-VMN6TP
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Package
8SOIC N
Cell Type
NOR
Density
8 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3.3 V
Sector Size
64KByte x 16
Timing Type
Synchronous
Interface Type
Serial-SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25P80-VMN6TP
M25P80-VMN6TPTR
Q3580447
M25P80-VMN6TPTR
Q3580447
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P80-VMN6TP
Manufacturer:
Numonyx
Quantity:
22 500
Company:
Part Number:
M25P80-VMN6TP
Manufacturer:
MICRON44
Quantity:
2 163
Part Number:
M25P80-VMN6TP
Manufacturer:
ST
Quantity:
20 000
3
Figure 3.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
10/57
SPI Interface with
(CPOL, CPHA) =
CS3
(0, 0) or (1, 1)
SPI Bus Master
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in Standby mode and not transferring data:
Bus Master and memory devices on the SPI bus
Figure 3
one device is selected at a time, so only one device drives the Serial Data Output (Q) line at
a time, the other devices are high impedance. Resistors R (represented in
that the M25P80 is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at
the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the t
typical value of R is 100K Ω, assuming that the time constant R*C
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
CS2 CS1
CPOL=0, CPHA=0
CPOL=1, CPHA=1
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
shows an example of three devices connected to an MCU, on an SPI bus. Only
SDO
SDI
SCK
R
R
C Q D
S
SPI Memory
Device
W
V
CC
HOLD
V
R
SS
C Q D
S
SPI Memory
Device
Figure
W
V
HOLD
CC
SHCH
V
4, is the clock polarity when the
R
SS
requirement is met). The
p
C Q D
S
(C
SPI Memory
p
Device
= parasitic
W
Figure
V
CC
HOLD
AI12836b
V
SS
3) ensure
V
V
CC
SS