M25P80-VMN6TP NUMONYX, M25P80-VMN6TP Datasheet - Page 23
![IC FLASH 8MBIT 75MHZ 8SOIC](/photos/7/28/72830/m25p80-vmn6tp_sml.jpg)
M25P80-VMN6TP
Manufacturer Part Number
M25P80-VMN6TP
Description
IC FLASH 8MBIT 75MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P80-VMP6G.pdf
(57 pages)
Specifications of M25P80-VMN6TP
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Package
8SOIC N
Cell Type
NOR
Density
8 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3.3 V
Sector Size
64KByte x 16
Timing Type
Synchronous
Interface Type
Serial-SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25P80-VMN6TP
M25P80-VMN6TPTR
Q3580447
M25P80-VMN6TPTR
Q3580447
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P80-VMN6TP
Manufacturer:
Numonyx
Quantity:
22 500
Company:
Part Number:
M25P80-VMN6TP
Manufacturer:
MICRON44
Quantity:
2 163
Part Number:
M25P80-VMN6TP
Manufacturer:
ST
Quantity:
20 000
6.4
6.4.1
6.4.2
6.4.3
6.4.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in
Table 6.
The status and control bits of the Status Register are as follows:
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, both Block Protect
(BP2, BP1, BP0) bits are 0.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and
the Write Status Register (WRSR) instruction is no longer accepted for execution.
Status Register Write Protect
SRWD
b7
Status Register format
0
0
BP2
BP1
Block Protect bits
Write Enable Latch bit
BP0
Table
Figure
WEL
Write In Progress bit
2) becomes
10.
WIP
b0
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