M25P80-VMN6TP NUMONYX, M25P80-VMN6TP Datasheet - Page 34
![IC FLASH 8MBIT 75MHZ 8SOIC](/photos/7/28/72830/m25p80-vmn6tp_sml.jpg)
M25P80-VMN6TP
Manufacturer Part Number
M25P80-VMN6TP
Description
IC FLASH 8MBIT 75MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P80-VMP6G.pdf
(57 pages)
Specifications of M25P80-VMN6TP
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Package
8SOIC N
Cell Type
NOR
Density
8 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3.3 V
Sector Size
64KByte x 16
Timing Type
Synchronous
Interface Type
Serial-SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25P80-VMN6TP
M25P80-VMN6TPTR
Q3580447
M25P80-VMN6TPTR
Q3580447
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P80-VMN6TP
Manufacturer:
Numonyx
Quantity:
22 500
Company:
Part Number:
M25P80-VMN6TP
Manufacturer:
MICRON44
Quantity:
2 163
Part Number:
M25P80-VMN6TP
Manufacturer:
ST
Quantity:
20 000
6.12
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Release from Deep Power-down and Read Electronic
Signature (RES)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down and Read Electronic Signature (RES)
instruction. Executing this instruction takes the device out of the Deep Power-down mode.
The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic
Signature, whose value for the M25P80 is 13h.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic
Signature that is read by the Read Identifier (RDID) instruction. The old-style Electronic
Signature is supported for reasons of backward compatibility, only, and should not be used
for new designs. New designs should, instead, make use of the JEDEC 16-bit Electronic
Signature, and the Read Identifier (RDID) instruction.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release
from Deep Power-down and Read Electronic Signature (RES) instruction always provides
access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep
Power-down mode has not been entered.
Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while
an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no
effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed
by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge
of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out
on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock
(C).
The instruction sequence is shown in
The Release from Deep Power-down and Read Electronic Signature (RES) instruction is
terminated by driving Chip Select (S) High after the Electronic Signature has been read at
least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is
driven Low, cause the Electronic Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Standby
Power mode is immediate. If the device was previously in the Deep Power-down mode,
though, the transition to the Standby Power mode is delayed by t
must remain High for at least t
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device,
but before the whole of the 8-bit Electronic Signature has been transmitted for the first time
(as shown in
device was not previously in the Deep Power-down mode, the transition to the Standby
Power mode is immediate. If the device was previously in the Deep Power-down mode,
though, the transition to the Standby Power mode is delayed by t
must remain High for at least t
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Figure
19), still insures that the device is put into Standby Power mode. If the
RES2
RES1
(max), as specified in
(max), as specified in
Figure
18.
Table
Table
15. Once in the Standby
15. Once in the Standby
RES2
RES1
, and Chip Select (S)
, and Chip Select (S)