M25PE16-VMW6TG NUMONYX, M25PE16-VMW6TG Datasheet - Page 13
![IC FLASH 16MBIT 75MHZ 8SOIC](/photos/7/28/72835/m25pe16-vmw6tg_sml.jpg)
M25PE16-VMW6TG
Manufacturer Part Number
M25PE16-VMW6TG
Description
IC FLASH 16MBIT 75MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M45PE16-VMP6TG.pdf
(58 pages)
Specifications of M25PE16-VMW6TG
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
16M (2M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Package
8SOIC W
Cell Type
NOR
Density
16 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3.3 V
Sector Size
64KByte x 32
Timing Type
Synchronous
Interface Type
Serial-SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25PE16-VMW6TGTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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Quantity:
14 500
Company:
Part Number:
M25PE16-VMW6TG
Manufacturer:
Numonyx
Quantity:
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M25PE16
4.3
4.4
4.5
4.6
A fast way to modify data
The page program (PP) instruction provides a fast way of modifying data (up to 256
contiguous bytes at a time), provided that it only involves resetting bits to ‘0’ that had
previously been set to ‘1’.
This might be:
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see
program
characteristics (75 MHz
Polling during a write, program or erase cycle
A further improvement in the time to write (PW, WRSR), program (PP) or erase (SE, SSE or
BE) can be achieved by not waiting for the worst case delay (t
t
program can monitor its value, polling it to establish when the previous cycle is complete.
Reset
An internal power-on reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset) Low during the power-on process, and only
driving it High when V
Active power, standby power and deep power-down modes
When Chip Select (S) is Low, the device is selected, and in the active power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the active power
mode until all internal cycles have completed (program, erase, write). The device then goes
in to the standby power mode. The device consumption drops to I
The deep power-down mode is entered when the specific instruction (the deep power-down
(DP) instruction) is executed. The device consumption drops further to I
mode, only the release from deep power-down instruction is accepted. All other instructions
are ignored. The device remains in the deep power-down mode until the release from deep
power-down instruction is executed. This can be used as an extra software protection
mechanism, when the device is not in active use, to protect the device from inadvertent
write, program or erase instructions.
BE
). The write in progress (WIP) bit is provided in the status register so that the application
when the designer is programming the device for the first time
when the designer knows that the page has already been erased by an earlier page
erase (PE), subsector erase (SSE), sector erase (SE) or bulk erase (BE) instruction.
This is useful, for example, when storing a fast stream of data, having first performed
the erase cycle when time was available
when the designer knows that the only changes involve resetting bits to 0 that are still
set to ‘1’. When this method is possible, it has the additional advantage of minimizing
the number of unnecessary erase operations, and the extra stress incurred by each
page.
(PP),
Table 18: AC characteristics (50 MHz
CC
operation)).
has reached the correct voltage level, V
operation), and
W
, t
CC
PW
CC1
(min).
, t
Table 19: AC
Section 6.10: Page
.
PP
Operating features
CC2
, t
PE
. When in this
, t
SE
, t
SSE
or
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