IDT71T75702S85PFG IDT, Integrated Device Technology Inc, IDT71T75702S85PFG Datasheet - Page 12

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IDT71T75702S85PFG

Manufacturer Part Number
IDT71T75702S85PFG
Description
IC SRAM 18MBIT 85NS 100TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71T75702S85PFG

Format - Memory
RAM
Memory Type
SRAM - Synchronous ZBT
Memory Size
18M (512K x 36)
Speed
85ns
Interface
Parallel
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
71T75702S85PFG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT71T75702S85PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71T75702S85PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71T75702S85PFGI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Cycle
Cycle
n+2
n+3
n+4
n+5
n+6
n+7
n+2
n+3
n+4
n+5
n+6
n+7
n+1
n+1
n
n
2
2
timing transition is identical to CE
timing transition is identical to CE
Address
Address
A
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
0
2
3
4
0
2
3
4
1
1
R/
R/
H
X
H
X
X
H
H
H
X
X
X
L
L
L
L
L
1
1
ADV/
ADV/
signal. CE
signal. CE
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
2
2
timing transition is identical but inverted to the CE
timing transition is identical but inverted to the CE
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
1
1
(2)
(2)
L
H
L
H
H
L
L
L
L
H
L
H
H
L
L
L
6.42
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
12
x
x
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
I/O
I/O
Q
Q
Q
Q
Q
D
D
D
Q
D
X
X
X
X
X
X
0
2
3
Commercial and Industrial Temperature Ranges
0
0
0
2
3
1
1
1
1
and CE
and CE
Comments
Clock n+1 Ignored
Clock Ignored. Data Q
Clock Ignored. Data Q
Comments
Clock n+1 Ignored.
Clock Ignored.
Clock Ignored.
Address A
Address A
Address A
Address A
Address A
Address A
Write data D
Write Data D
Write Data D
Write Data D
2
2
signals.
signals.
0
0
1
2
3
0
Read out, Load A
Read out, Load A
Read out, Load A
Read out, Load A
0
and Control meet setup
and Control meet setup.
1
2
3
, Load A
, Load A
, Load A
, Load A
1
2
3
4
0
0
.
is on the bus.
is on the bus.
1
2
3
4
5319 tbl 17
5319 tbl 18

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