IDT71T75702S85PFG IDT, Integrated Device Technology Inc, IDT71T75702S85PFG Datasheet - Page 5

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IDT71T75702S85PFG

Manufacturer Part Number
IDT71T75702S85PFG
Description
IC SRAM 18MBIT 85NS 100TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71T75702S85PFG

Format - Memory
RAM
Memory Type
SRAM - Synchronous ZBT
Memory Size
18M (512K x 36)
Speed
85ns
Interface
Parallel
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
71T75702S85PFG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT71T75702S85PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71T75702S85PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71T75702S85PFGI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. During production testing, the case temperature equals the ambient temperature.
NOTES:
1. Pins 14 and 66 do not have to be connected directly to V
2. Pin 16 does not have to be connected directly to V
3. Pins 38, 39 and 43 will be pulled internally to V
4. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device.
Commerical
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Industrial
several settings are possible. Pins 38, 39 and 43 could be tied to V
TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.
Grade
-40 °C to +85 °C
0 °C to +70 °C
Temperature
Ambient
V
V
V
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DD
SS
DDQ
V
V
DDQ
V
V
DDQ
V
V
DDQ
(1)
DD
SS
SS
SS
SS
SS
P3
P4
16
17
18
19
20
21
22
23
(1)
(2)
24
25
26
27
28
29
30
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
OV
OV
SS
100 99 98 97 96 95 94 93 92 91 90
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2.5V ± 5%
2.5V ± 5%
DD
V
DD
if not actively driven. To disable the TAP controller without interfering with normal operation,
DD
as long as the input voltage is
SS
as long as the input voltage is
2.5V ± 5%
2.5V ± 5%
V
DDQ
5319 tbl 05
DD
or V
6.42
SS
5
and pin 42 should be left unconnected. Or all JTAG inputs (TMS,
89 88
87 86 85 84 83 82 81
V
IH
.
V
IL
.
Commercial and Industrial Temperature Ranges
80
79
78
77
76
75
74
73
71
69
67
66
65
64
62
61
60
59
58
57
56
54
53
52
72
70
68
63
55
51
5319 drw 02
I/O
I/O
V
I/O
I/O
I/O
I/O
I/O
I/O
V
V
V
V
I/O
I/O
I/O
I/O
V
V
V
V
I/O
I/O
V
V
I/O
I/O
ZZ
I/O
I/O
DDQ
SS
SS
DDQ
SS
SS
DD
DDQ
SS
SS
DDQ
15
14
13
12
11
10
9
8
5
4
3
2
7
6
1
0
P1
P2
(1)
,

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