IDT71T75702S85PFG IDT, Integrated Device Technology Inc, IDT71T75702S85PFG Datasheet - Page 8

• Manufacturer Part Number: IDT71T75702S85PFG
• Description: IC SRAM 18MBIT 85NS 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT71T75702S85PFG

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous ZBT
• Memory Size: 18M (512K x 36)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 71T75702S85PFG

NOTES:
1. L = V
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
3. Deselect cycle is initiated when either (CE
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
5. To select the chip requires CE
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
NOTES:
1. L = V
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
READ
NO WRITE
First Address
Second Address
Fourth Address
WRITE ALL BYTES
WRITE BYTE 1 (I/O[0:7], I/O
WRITE BYTE 2 (I/O[8:15], I/O
WRITE BYTE 3 (I/O[16:23], I/O
WRITE BYTE 4 (I/O[24:31], I/O
Third Address
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
tri-state one cycle after deselect is initiated.
I/Os remains unchanged.
L
L
L
L
L
L
H
IL
IL
, H = V
, H = V
R/
X
X
X
X
X
L
H
(1)
IH
IH
, X = Don’t Care.
, X = Don’t Care.
1
,
X
X
H
X
X
L
L
2
P1
(5)
1
P2
)
= L, CE
P3
P4
OPERATION
(2)
)
(2)
)
)
(2,3)
(2,3)
ADV/
2
= L and CE
L
L
H
H
L
H
X
1
, or CE
2
Valid
Valid
= H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
2
X
X
X
X
X
x
is sampled high or CE
A1
0
0
1
1
Sequence 1
ADDRESS
External
External
Internal
Internal
USED
X
X
X
A0
0
0
1
1
2
6.42
LBO
is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
8
DESELECT / NOOP
PREVIOUS CYCLE
A1
LOAD WRITE /
BURST WRITE
LOAD READ /
BURST READ
0
0
1
1
R/
Sequence 2
H
L
L
L
L
L
L
X
X
X
X
A0
0
0
1
1
Commercial and Industrial Temperature Ranges
X
L
L
H
H
H
H
1
(Advance burst counter)
(Advance burst counter)
DESELECT or STOP
A1
0
0
1
1
CURRENT CYCLE
Sequence 3
BURST WRITE
BURST READ
LOAD WRITE
LOAD READ
SUSPEND
NOOP
X
L
H
L
H
H
H
2
A0
0
0
1
1
(4)
(3)
(2)
(2)
X
L
H
H
L
H
H
3
(3)
A1
0
0
1
1
Sequence 4
(One cycle later)
Previous Value
D
Q
Q
HIZ
HIZ
I/O
D
(7)
(7)
(7)
(7)
X
H
H
H
H
L
L
5319 tbl 08
5319 tbl 09
5319 tbl 10
A0
4
0
0
1
1
(3)