UPD44164362AF5-E33-EQ2 Renesas Electronics America, UPD44164362AF5-E33-EQ2 Datasheet - Page 11

• Manufacturer Part Number: UPD44164362AF5-E33-EQ2
• Description: SRAM DDRII 18MBIT CIO 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44164362AF5-E33-EQ2

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (512K x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power-on Sequence
V
1. Clock starts after V
(a)
(b)
(c)
DD
The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after
The clock is supplied from a controller.
/V
DD
V
V
V
DD
DD
DD
Q stable and when starting the clock before V
/V
Clock
DLL#
/V
Note Input a stable clock from the start.
Clock
DLL#
/V
DLL#
Clock
DD
DD
DD
Q
Q
Q
DD
/V
μ
DD
Clock Start
Clock Start
Clock Start
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Q stable
20 ns (MIN.)
(level, frequency)
(level, frequency)
Unstable Clock
Unstable Clock
Note
V
V
Data Sheet M19866EJ1V0DS
DD
DD
/V
/V
Fix HIGH (or tied to V
DD
DD
Q Stable (< ±0.1 V DC per 50 ns)
Q Stable (< ±0.1 V DC per 50 ns)
30 ns. (MIN.)
Clock Stop
V
DD
DD
/V
Fix HIGH (or tied to V
DD
/V
1,024 cycles or more
Q Stable (< ±0.1 V DC per 50 ns)
DD
Q stable.
Stable Clock
Switched to HIGH after Clock is stable.
DD
Q)
1,024 cycles or more
DD
Q)
Stable Clock
1,024 cycles or more
Stable Clock
Normal Operation
Start
Normal Operation
Start
Normal Operation
Start
11