UPD44164362AF5-E33-EQ2 Renesas Electronics America, UPD44164362AF5-E33-EQ2 Datasheet - Page 21

• Manufacturer Part Number: UPD44164362AF5-E33-EQ2
• Description: SRAM DDRII 18MBIT CIO 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44164362AF5-E33-EQ2

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (512K x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
Remarks 1. This parameter is sampled.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
3. V
5. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from
6. This is a synchronous device. All addresses, data and control lines must meet the specified setup
4. K input is monitored for this operation. See below for the timing.
K
(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.5 clock in
this operation. The AC/DC characteristics cannot be guaranteed, however.
DLL/PLL lock time begins once V
It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.
or
K
2. Test conditions as specified with the output loading as shown in AC Test Conditions
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. V
(MAX.) indicates a peak-to-peak value.
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
and hold times for all latching clock edges.
DD
unless otherwise noted.
slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention.
DD
Q is 1.5 V DC.
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
TKC reset
TKC reset
DD
Data Sheet M19866EJ1V0DS
and input clock are stable.
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