UPD44164362AF5-E33-EQ2 Renesas Electronics America, UPD44164362AF5-E33-EQ2 Datasheet - Page 32

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UPD44164362AF5-E33-EQ2

Manufacturer Part Number
UPD44164362AF5-E33-EQ2
Description
SRAM DDRII 18MBIT CIO 165-PBGA
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD44164362AF5-E33-EQ2

Format - Memory
RAM
Memory Type
SRAM - Synchronous, DDR II
Memory Size
18M (512K x 36)
Speed
300MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
TAP Controller State Diagram
1
0
Disabling the Test Access Port
operation of the device, TCK must be tied to V
them to V
when the TAP controller is not used.
32
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal
DD
via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected also
Test-Logic-Reset
Run-Test / Idle
0
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
1
Data Sheet M19866EJ1V0DS
1
0
SS
to preclude mid level inputs. TDI and TMS may be left open but fix
Select-DR-Scan
Capture-DR
Update-DR
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
1
0
0
1
0
1
1
0
1
1
0
0
1
0
Select-IR-Scan
Capture-IR
Update-IR
Pause-IR
Exit1-IR
Exit2-IR
Shift-IR
1
0
0
1
0
1
1
0
1
1
0
0

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