AT45DB041D-SSU Atmel, AT45DB041D-SSU Datasheet - Page 21
![IC FLASH 4MBIT 66MHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
AT45DB041D-SSU
Manufacturer Part Number
AT45DB041D-SSU
Description
IC FLASH 4MBIT 66MHZ 8SOIC
Manufacturer
Atmel
Specifications of AT45DB041D-SSU
Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
4M (2048 pages x 264 bytes)
Speed
66MHz
Interface
SPI, RapidS
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Density
4Mb
Access Time (max)
6ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Supply Current
15mA
Mounting
Surface Mount
Pin Count
8
Architecture
Sectored
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
15 mA
Mounting Style
SMD/SMT
Organization
64 KB x 8
Memory Configuration
2048 Pages X 256 Bytes
Clock Frequency
50MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT45DB041D-SSU
Manufacturer:
ATMEL
Quantity:
12 000
Part Number:
AT45DB041D-SSU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT45DB041D-SSU-2.5
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
10.2.2
11. Additional Commands
11.1
11.2
3595P–DFLASH–09/09
Main Memory Page to Buffer Transfer
Main Memory Page to Buffer Compare
Reading the Security Register
The Security Register can be read by first asserting the CS pin and then clocking in an opcode
of 77H followed by three dummy bytes. After the last don't care bit has been clocked in, the con-
tent of the Security Register can be clocked out on the SO pins. After the last byte of the
Security Register has been read, additional pulses on the SCK pin will simply result in undefined
data being output on the SO pins.
Deasserting the CS pin will terminate the Read Security Register operation and put the SO pins
into a high-impedance state.
Figure 10-4. Read Security Register
A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start
the operation for the DataFlash standard page size (264 bytes), a 1-byte opcode, 53H for buffer
1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes com-
prised of 4 don’t care bits, 11 page address bits (PA10 - PA0), which specify the page in main
memory that is to be transferred, and 9 don’t care bits. To perform a main memory page to buffer
transfer for the binary page size (256 bytes), the opcode 53H for buffer 1 or 55H for buffer 2,
must be clocked into the device followed by three address bytes consisting of 5 don’t care bits,
11 page address bits (A18 - A8) which specify the page in the main memory that is to be trans-
ferred, and 8 don’t care bits. The CS pin must be low while toggling the SCK pin to load the
opcode and the address bytes from the input pin (SI). The transfer of the page of data from the
main memory to the buffer will begin when the CS pin transitions from a low to a high state. Dur-
ing the transfer of a page of data (t
transfer has been completed.
A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate
the operation for the DataFlash standard page size, a 1-byte opcode, 60H for buffer 1 and 61H
for buffer 2, must be clocked into the device, followed by three address bytes consisting of
4 don’t care bits, 11 page address bits (PA10 - PA0) that specify the page in the main memory
that is to be compared to the buffer, and 9 don’t care bits. To start a main memory page to buffer
compare for a binary page size, the opcode 60H for buffer 1 or 61H for buffer 2, must be clocked
into the device followed by three address bytes consisting of 5 don’t care bits, 11 page address
bits (A18 - A8) that specify the page in the main memory that is to be compared to the buffer,
and 8 don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode and
CS
SO
SI
Each transition
represents 8 bits
Opcode
X
XFR
), the status register can be read to determine whether the
X
X
Data Byte
n
Data Byte
n + 1
AT45DB041D
Data Byte
n + x
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