AT45DB041D-SSU Atmel, AT45DB041D-SSU Datasheet - Page 22

• Manufacturer Part Number: AT45DB041D-SSU
• Description: IC FLASH 4MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB041D-SSU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 4M (2048 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Density: 4Mb
• Access Time (max): 6ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Architecture: Sectored
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 8
• Memory Configuration: 2048 Pages X 256 Bytes
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3
11.4
22
Auto Page Rewrite
Status Register Read
AT45DB041D
the address bytes from the input pin (SI). On the low-to-high transition of the CS pin, the data
bytes in the selected main memory page will be compared with the data bytes in buffer 1 or buf-
fer 2. During this time (t
of the compare operation, bit 6 of the status register is updated with the result of the compare.
This mode is only needed if multiple bytes within a page or multiple pages of data are modified in
a random fashion within a sector. This mode is a combination of two operations: Main Memory
Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of
data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data
(from buffer 1 or buffer 2) is programmed back into its original page of main memory. To start the
rewrite operation for the DataFlash standard page size (264 bytes), a 1-byte opcode, 58H for
buffer 1 or 59H for buffer 2, must be clocked into the device, followed by three address bytes
comprised of 4 don’t care bits, 11 page address bits (PA10-PA0) that specify the page in main
memory to be rewritten and 9 don’t care bits. To initiate an auto page rewrite for a binary page
size (256 bytes), the opcode 58H for buffer 1 or 59H for buffer 2, must be clocked into the device
followed by three address bytes consisting of 5 don’t care bits, 11 page address bits (A18 - A8)
that specify the page in the main memory that is to be written and 8 don’t care bits. When a low-
to-high transition occurs on the CS pin, the part will first transfer data from the page in main
memory to a buffer and then program the data from the buffer back into same page of main
memory. The operation is internally self-timed and should take place in a maximum time of t
During this time, the status register will indicate that the part is busy.
If a sector is programmed or reprogrammed sequentially page by page, then the programming
algorithm shown in
page or several pages are programmed randomly in a sector, then the programming algorithm
shown in
updated/rewritten at least once within every 10,000 cumulative page erase/program operations
in that sector.
The status register can be used to determine the device’s ready/busy status, page size, a Main
Memory Page to Buffer Compare operation result, the Sector Protection status or the device
density. The Status Register can be read at any time, including during an internally self-timed
program or erase operation. To read the status register, the CS pin must be asserted and the
opcode of D7H must be loaded into the device. After the opcode is clocked in, the 1-byte status
register will be clocked out on the output pin (SO), starting with the next clock cycle. The data in
the status register, starting with the MSB (bit 7), will be clocked out on the SO pin during the next
eight clock cycles. After the one byte of the status register has been clocked out, the sequence
will repeat itself (as long as CS remains low and SCK is being toggled). The data in the status
register is constantly updated, so each repeating sequence will output new data.
Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is
not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy
state. Since the data in the status register is constantly updated, the user must toggle SCK pin to
check the ready/busy status. There are several operations that can cause the device to be in a
busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buf-
fer to Main Memory Page Program, Main Memory Page Program through Buffer, Page Erase,
Block Erase, Sector Erase, Chip Erase and Auto Page Rewrite.
Figure 25-2 (page
Figure 25-1 (page
COMP
), the status register will indicate that the part is busy. On completion
47) is recommended. Each page within a sector must be
46) is recommended. Otherwise, if multiple bytes in a
3595P–DFLASH–09/09
EP
.