MT46H8M16LFCF-10 Micron Technology Inc, MT46H8M16LFCF-10 Datasheet - Page 52

• Manufacturer Part Number: MT46H8M16LFCF-10
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M16LFCF-10

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 60-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes
PDF: 09005aef822b7e27/Source: 09005aef822b7dd6
MT46H8M16LFB_2.fm - Rev. A 5/06 EN
10. I
11. Enables on-chip refresh and address counters.
12. I
13. This parameter is sampled. V
14. Fast command/address input slew rate ≥ 1V/ns. Slow command/address input slew
1. All voltages referenced to Vss.
2. All parameters assume proper device initialization.
3. Tests for AC timing, I
4. Outputs measured with equivalent load:
5. Timing and I
6. All AC timings assume an input slew rate of 1V/ns.
7. CAS latency definition: for CL = 2, the first data element is valid at (
8. V
9. The value of V
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified.
I/O
I/O
I/O
but input timing is still referenced to V
The output timing reference voltage level is V
clock at which the READ command was registered; for CL = 3, the first data element is
valid at (2 ×
registered.
level on CK#.
track variations in the DC level of the same.
V
mum cycle time for CL = 3 with the outputs open.
after test condition is met.
T
I/O balls, reflecting the fact that they are matched in loading.
rate ≥ 0.5V/ns. If the slew rate is less than 0.5V/ns, timing must be derated:
additional 50ps (pending) per each 100mV/ns reduction in slew rate from the 0.5V/
ns.
4.5V/ns, functionality is uncertain.
DD
DD
A
ID
DD
Quarter-drive strength
= 25ºC, V
t
Half-drive strength
Full-drive strength
is the magnitude of the difference between the input level on CK and the input
is dependent on cycle rate, and may be affected by output loading if V
specifications are tested after the device is properly initialized, and is averaged
IH has 0ps added (pending); that is, it remains constant. If the slew rate exceeds
Q are supplied from the same source. Specified values are obtained with mini-
50
50
50
OUT
t
DD
CK +
IX
(
tests may use a V
is expected to equal V
DC
t
AC) after the first clock at which the READ command was
) = V
20 pF
10 pF
5 pF
DD
, and electrical AC and DC characteristics may be conducted
DD
Q/2, V
52
DD
= +1.8 ±0.1V, V
OUT
IL
128Mb: 8 Meg x 16 Mobile DDR SDRAM
-to-V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(peak-to-peak) = 0.2V. DM input is grouped with
DD
DD
IH
Q/2 of the transmitting device and must
Q/2 (or to the crossing point for CK/CK#).
swing of up to 1.5V in the test environment,
DD
DD
Q/2.
Q = +1.8 ±0.1V, f = 100 MHz,
©2006 Micron Technology, Inc. All rights reserved.
t
CK +
t
AC) after the
DD
t
IS has an
and
Advance
Notes