MT46V8M16TG-75:D Micron Technology Inc, MT46V8M16TG-75:D Datasheet - Page 17
![IC DDR SDRAM 128MBIT 66TSOP](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V8M16TG-75:D
Manufacturer Part Number
MT46V8M16TG-75:D
Description
IC DDR SDRAM 128MBIT 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V16M8TG-6T_LD_TR.pdf
(81 pages)
Specifications of MT46V8M16TG-75:D
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
128M (8Mx16)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
140mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46V8M16TG-75:D
Manufacturer:
MICRON
Quantity:
20 000
Figure 8:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
Transmitter
Input Voltage Waveform
Notes:
1. V
2. V
3. Numbers in diagram reflect nominal values utilizing circuit below for all devices other than
-5B.
OH
OL
(MAX) with test load is 0.373V.
25Ω
(MIN) with test load is 1.927V.
V
V
V
V
VssQ
OL
TT
DD
OH
1.560V
1.400V
1.300V
1.275V
1.250V
1.225V
1.200V
1.100V
0.940V
V
25Ω
IN
Q (2.3V MIN)
System noise margin (power/ground,
crosstalk, signal integrity attenuation)
(MAX) (0.83V
(MIN) (1.670V
(
AC
between
and
) - provides margin
V
termination)
IL
(
AC
Reference
point
V
)
2
OL
1
for SSTL_2
for SSTL_2 termination)
(MAX)
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Electrical Specifications – DC and AC
128Mb: x4, x8, x16 DDR SDRAM
Receiver
©2004 Micron Technology, Inc. All rights reserved.
V
V
V
V
V
V
V
V
IH
IH
REF
REF
REF
REF
IL
IL
(
(
(
(
DC
AC
AC
DC
+ AC noise
+ DC error
- DC error
- AC noise
)
)
)
)