MT46V8M16TG-75:D Micron Technology Inc, MT46V8M16TG-75:D Datasheet - Page 30
![IC DDR SDRAM 128MBIT 66TSOP](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V8M16TG-75:D
Manufacturer Part Number
MT46V8M16TG-75:D
Description
IC DDR SDRAM 128MBIT 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V16M8TG-6T_LD_TR.pdf
(81 pages)
Specifications of MT46V8M16TG-75:D
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
128M (8Mx16)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
140mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46V8M16TG-75:D
Manufacturer:
MICRON
Quantity:
20 000
Figure 13:
Figure 14:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
Reduced Drive Pull-Down Characteristics
Reduced Drive Pull-Up Characteristics
40. The voltage levels used are derived from a minimum V
41.
42. V
43.
39d. The driver pull-up current variation, within nominal voltage and temperature
39e. The full ratio variation of the MAX-to-MIN pull-up and pull-down current should
39f. The full ratio variation of the nominal pull-up to pull-down current should be
80
70
60
50
40
30
20
10
load. In practice, the voltage levels obtained from a properly terminated bus will pro-
vide significantly different voltage values.
V
width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) =
for a pulse width ≤ 3ns, and the pulse width can not be greater than 1/3 of the cycle
rate.
t
prevail over
HZ (MAX) will prevail over
0
-10
-20
-30
-40
-50
-60
-70
-80
IH
DD
0 . 0
0
0.0
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 14 on page 30.
be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V at
the same voltage and temperature.
unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
overshoot: V
and V
DD
0 . 5
t
0.5
DQSCK (MIN) +
Q must track each other.
IH
(MAX) = V
1 . 0
1.0
V
DD
V
Q - V
OUT
30
t
(V)
OUT
DQSCK (MAX) +
t
RPRE (MAX) condition.
DD
(V)
1 . 5
1.5
Q + 1.5V for a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Electrical Specifications – DC and AC
2.0
2.0
128Mb: x4, x8, x16 DDR SDRAM
t
RPST (MAX) condition.
pulse width ≤ 3ns, and the pulse
2.5
2.5
DD
level and the referenced test
©2004 Micron Technology, Inc. All rights reserved.
t
LZ (MIN) will
–
1.5V