MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 100
![IC DDR3 SDRAM 1GBIT 78FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J256M4HX-15E:D TR
Manufacturer Part Number
MT41J256M4HX-15E:D TR
Description
IC DDR3 SDRAM 1GBIT 78FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J256M4HX-15E:D TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (256M x 4)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-FBGA
Organization
256Mx4
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
220mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 47: Change Frequency During Precharge Power-Down
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
DQS, DQS#
Command
Address
ODT
CK#
CKE
DM
DQ
CK
NOP
T0
t AOFPD/ t AOF
t IH
t CH
t CK
power-down mode
Notes:
Enter precharge
t CL
t IS
NOP
Previous clock frequency
T1
t CPDED
been satisfied, the DLL must be reset via the MRS. Depending on the new clock
frequency, additional MRS commands may need to be issued. During the DLL lock time,
R
ready to operate with a new clock frequency. This process is depicted in Figure 47.
1. Applicable for both slow-exit and fast-exit precharge power-down modes.
2.
3. If the R
High-Z
High-Z
TT
t
tion (ODT)" on page 160 for exact requirements).
power-down mode, the ODT signal must be continuously registered LOW ensuring R
an off state. If the R
charge power-down mode, R
tered either LOW or HIGH in this case.
AOFPD and
_
t CKSRE
NOM
NOP
T2
and R
TT
_
NOM
t
Ta0
TT
AOF must be satisfied and outputs High-Z prior to T1 (see "On-Die Termina-
feature was enabled in the mode register prior to entering precharge
t CKE
_
Frequency
WR
change
TT
Tb0
must remain in an off state. After the DLL lock time, the DRAM is
_
NOM
feature was disabled in the mode register prior to entering pre-
100
t CKSRX
TT
Tc0
t IH
will remain in the off state. The ODT signal can be regis-
t CH
b
t CK
power-down mode
b
Exit precharge
t CL
b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t IS
NOP
Tc1
1Gb: x4, x8, x16 DDR3 SDRAM
New clock frequency
NOP
t XP
Td0
t CH
b
t CK
b
t CL
DLL RESET
b
MRS
Td1
©2006 Micron Technology, Inc. All rights reserved.
Indicates A Break in
Time Scale
t DLLK
NOP
Te0
t IH
t CH
Commands
b
t CK
b
t CL
b
t IS
Valid
Valid
Te1
Don’t Care
TT
is in
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