MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 111

• Manufacturer Part Number: MT41J256M4HX-15E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M4HX-15E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Organization: 256Mx4
• Density: 1Gb
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 220mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 68:
DLL RESET
Write Recovery
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
Length
4 chop
Burst
8
Burst Order
WRITE
READ/
WRITE
WRITE
READ
READ
Notes:
Starting Column
1. Internal READ and WRITE operations start at the same point in time for BC4 as they do for
2. Z = Data and strobe output drivers are in tristate.
3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input pins.
4. X = “Don’t Care.”
DLL RESET is defined by MR0[8] (see Figure 54 on page 110). Programming MR0[8] to
“1” activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a
value of “0” after the DLL RESET function has been initiated.
Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held
stable for 512 (
allow time for the internal clock to be synchronized with the external clock. Failing to
wait for synchronization to occur may result in invalid output timing specifications,
such as
WRITE recovery time is defined by MR0[11:9] (see Figure 54 on page 110). Write recovery
values of 5, 6, 7, 8, 10, or 12 may be used by programming MR0[11:9]. The user is
required to program the correct value of write recovery and is calculated by dividing
(ns) by
roundup (
(A[2, 1, 0])
Address
BL8.
V V V
0 V V
1 V V
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
t
t
CK (ns) and rounding up a noninteger value to the next integer: WR (cycles) =
DQSCK timings.
t
WR [ns]/
t
DLLK) clock cycles before a READ command can be issued. This is to
Burst Type = Sequential
t
CK [ns]).
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, Z, Z, Z, Z
1, 2, 3, 0, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
3, 0, 1, 2, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
5, 6, 7, 4, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
7, 4, 5, 6, Z, Z, Z, Z
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
(Decimal)
111
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst Type = Interleaved
1Gb: x4, x8, x16 DDR3 SDRAM
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, Z, Z, Z, Z
1, 0, 3, 2, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
3, 2, 1, 0, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
5, 4, 7, 6, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
7, 6, 5, 4, Z, Z, Z, Z
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
(Decimal)
©2006 Micron Technology, Inc. All rights reserved.
Operations
Notes
1, 3, 4
1, 3, 4
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 3
1
1
1
1
1
1
1
1
t
WR