M25P05-AVMN6T NUMONYX, M25P05-AVMN6T Datasheet - Page 24

• Manufacturer Part Number: M25P05-AVMN6T
• Description: IC FLASH 512KBIT 40MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMN6T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 40MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1621-2

M25P05-A
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction
is the only way to put the device in the lowest con-
sumption mode (the Deep Power-down mode). It
can also be used as a software protection mecha-
nism, while the device is not in active use, as in
this mode, the device ignores all Write, Program
and Erase instructions.
Driving Chip Select (S) High deselects the device,
and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this
mode is not the Deep Power-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instruction,
subsequently reducing the standby current (from
I
To take the device out of Deep Power-down mode,
the Release from Deep Power-down and Read
Electronic Signature (RES) instruction must be is-
sued. No other instruction must be issued while
the device is in Deep Power-down mode.
The Release from Deep Power-down and Read
Electronic Signature (RES) instruction also allows
Figure 18. Deep Power-down (DP) Instruction Sequence
24/42
CC1
to I
S
C
D
CC2
, as specified in
0
1
Table
2
Instruction
3
13.).
4
5
6
7
the Electronic Signature of the device to be output
on Serial Data Output (Q).
The Deep Power-down mode automatically stops
at Power-down, and the device always Powers-up
in the Standby mode.
The Deep Power-down (DP) instruction is entered
by driving Chip Select (S) Low, followed by the in-
struction code on Serial Data Input (D). Chip Se-
lect (S) must be driven Low for the entire duration
of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise the Deep Power-down (DP) instruc-
tion is not executed. As soon as Chip Select (S) is
driven High, it requires a delay of t
supply current is reduced to I
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effects on the cycle that
is in progress.
t
Standby Mode
DP
Deep Power-down Mode
CC2
and the Deep
DP
Figure 18.
before the
AI03753D