M25P05-AVMN6T NUMONYX, M25P05-AVMN6T Datasheet - Page 9
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M25P05-AVMN6T
Manufacturer Part Number
M25P05-AVMN6T
Description
IC FLASH 512KBIT 40MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P05-AVMN6T.pdf
(42 pages)
Specifications of M25P05-AVMN6T
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
512K (64K x 8)
Speed
40MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-1621-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P05-AVMN6TP
Manufacturer:
FREESCALE
Quantity:
110
Company:
Part Number:
M25P05-AVMN6TP
Manufacturer:
NUMONYX
Quantity:
2 350
Part Number:
M25P05-AVMN6TP
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P05-AVMN6TP(25P05VP)
Manufacturer:
TI
Quantity:
13
Hold Condition
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence. However, taking this
signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently
in progress.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low (as shown in
ure
The Hold condition ends on the rising edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial
Clock (C) being Low, the Hold condition starts af-
ter Serial Clock (C) next goes Low. Similarly, if the
Figure 6. Hold Condition Activation
6.).
HOLD
C
(standard use)
Condition
Hold
Fig-
rising edge does not coincide with Serial Clock (C)
being Low, the Hold condition ends after Serial
Clock (C) next goes Low. (This is shown in
6.).
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip
Select (S) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of
the internal logic remains unchanged from the mo-
ment of entering the Hold condition.
If Chip Select (S) goes High while the device is in
the Hold condition, this has the effect of resetting
the internal logic of the device. To restart commu-
nication with the device, it is necessary to drive
Hold (HOLD) High, and then to drive Chip Select
(S) Low. This prevents the device from going back
to the Hold condition.
(non-standard use)
Condition
Hold
M25P05-A
AI02029D
Figure
9/42