M25P05-AVMN6T NUMONYX, M25P05-AVMN6T Datasheet - Page 25
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M25P05-AVMN6T
Manufacturer Part Number
M25P05-AVMN6T
Description
IC FLASH 512KBIT 40MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P05-AVMN6T.pdf
(42 pages)
Specifications of M25P05-AVMN6T
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
512K (64K x 8)
Speed
40MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-1621-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P05-AVMN6TP
Manufacturer:
FREESCALE
Quantity:
110
Company:
Part Number:
M25P05-AVMN6TP
Manufacturer:
NUMONYX
Quantity:
2 350
Part Number:
M25P05-AVMN6TP
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P05-AVMN6TP(25P05VP)
Manufacturer:
TI
Quantity:
13
Release from Deep Power-down and Read
Electronic Signature (RES)
To take the device out of Deep Power-down mode,
the Release from Deep Power-down and Read
Electronic Signature (RES) instruction must be is-
sued. No other instruction must be issued while
the device is in Deep Power-down mode.
The instruction can also be used to read, on Serial
Data Output (Q), the 8-bit Electronic Signature,
whose value for the M25P05-A is 05h.
Except while an Erase, Program or Write Status
Register cycle is in progress, the Release from
Deep Power-down and Read Electronic Signature
(RES) instruction always provides access to the 8-
bit Electronic Signature of the device, and can be
applied even if the Deep Power-down mode has
not been entered.
Any Release from Deep Power-down and Read
Electronic Signature (RES) instruction while an
Erase, Program or Write Status Register cycle is in
progress, is not decoded, and has no effect on the
cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code is followed by 3
dummy bytes, each bit being latched-in on Serial
Data Input (D) during the rising edge of Serial
Clock (C). Then, the 8-bit Electronic Signature,
stored in the memory, is shifted out on Serial Data
Output (Q), each bit being shifted out during the
falling edge of Serial Clock (C).
The instruction sequence is shown in
Figure 19. Release from Deep Power-down and Read Electronic Signature (RES) Instruction
Sequence and Data-Out Sequence
Note: The value of the 8-bit Electronic Signature, for the M25P05-A, is 05h.
S
C
D
Q
0
1
High Impedance
2
Instruction
3
4
5
6
7
MSB
23
8
22 21
9 10
3 Dummy Bytes
Figure 19.
3
28 29 30 31 32 33 34 35
2
1
0
The Release from Deep Power-down and Read
Electronic Signature (RES) instruction is terminat-
ed by driving Chip Select (S) High after the Elec-
tronic Signature has been read at least once.
Sending additional clock cycles on Serial Clock
(C), while Chip Select (S) is driven Low, cause the
Electronic Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is
put in the Standby Power mode. If the device was
not previously in the Deep Power-down mode, the
transition to the Standby Power mode is immedi-
ate. If the device was previously in the Deep Pow-
er-down mode, though, the transition to the
Standby Power mode is delayed by t
Chip Select (S) must remain High for at least
t
Standby Power mode, the device waits to be se-
lected, so that it can receive, decode and execute
instructions.
Driving Chip Select (S) High after the 8-bit instruc-
tion byte has been received by the device, but be-
fore the whole of the 8-bit Electronic Signature has
been transmitted for the first time (as shown in
ure
Standby Power mode. If the device was not previ-
ously in the Deep Power-down mode, the transi-
tion to the Standby Power mode is immediate. If
the device was previously in the Deep Power-
down mode, though, the transition to the Standby
Power mode is delayed by t
(S) must remain High for at least t
specified in
mode, the device waits to be selected, so that it
can receive, decode and execute instructions.
RES2
MSB
7
Electronic Signature Out
Deep Power-down Mode
20.), still ensures that the device is put into
6
(max), as specified in
5
4
Table 15.
3
36 37 38
2
1
0
Once in the Standby Power
t
Table 15.
RES1
RES2
, and Chip Select
RES1
Stand-by Mode
M25P05-A
Once in the
RES2
(max), as
AI04047C
, and
25/42
Fig-