PSD813F1A-90MI STMicroelectronics, PSD813F1A-90MI Datasheet - Page 31

• Manufacturer Part Number: PSD813F1A-90MI
• Description: IC FLASH 1MBIT 90NS 52QFP
• Manufacturer: STMicroelectronics

Specifications of PSD813F1A-90MI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1978

MEMORY SELECT SIGNALS
The main Flash (FSi), EEPROM (EESi), and
SRAM (RS0) memory select signals are all out-
puts of the DPLD. They are setup by entering
equations for them in PSDsoft Express. The fol-
lowing rules apply to the equations for the internal
chip select signals:
1. Flash memory and EEPROM sector select
2. Any main Flash memory sector must not be
3. An EEPROM sector must not be mapped in
4. SRAM, I/O, and Peripheral I/O spaces must
5. An EEPROM sector may overlap a main Flash
6. SRAM, I/O, and Peripheral I/O spaces may
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, EES0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 will always ac-
cess the SRAM. Any address in the range of EES0
greater than 87FFh (and less than 9FFFh) will au-
tomatically address EEPROM segment 0. Any ad-
dress greater than 9FFFh will access the Flash
memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of EE-
PROM segment 0 can not be accessed in this ex-
ample. Also note that an equation that defined FS1
to anywhere in the range of 8000h to BFFFh would
not be valid.
Figure
components. Any component on a higher level can
overlap and has priority over any component on a
lower level.
Table 12. VM Register
0 = disable
PIO mode
1= enable
PIO mode
PIO_EN
Bit 7
signals must not be larger than the physical
sector size.
mapped in the same memory space as
another Flash sector.
the same memory space as another EEPROM
sector.
not overlap.
memory sector. In case of overlap, priority will
be given to the EEPROM.
overlap any other memory sector. Priority will
be given to the SRAM, I/O, or Peripheral I/O.
11
shows the priority levels for all memory
not used not used
not used not used
Bit 6
Bit 5
0 = RD can’t
access
Flash
memory
1 = RD
access
Flash
memory
FL_Data
Bit 4
0 = RD can’t
access EEPROM
1 = RD access
EEPROM
EE_Data
Bit 3
using RD). Any of the memories within the PSD
can reside in either space or both spaces. This is
controlled through manipulation of the VM register
that resides in the PSD’s CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the microcontroller so that memory
mapping can be changed on-the-fly. For example,
I may wish to have SRAM and Flash in Data
Space at boot, and EEPROM in Program Space at
boot, and later swap EEPROM and Flash. This is
easily done with the VM register by using PSDsoft
Express to configure it for boot up and having the
microcontroller change it when desired. Table
describes the VM Register.
Figure 11. Priority Level of Memory and I/O
Components
Components on the same level must not overlap.
Level one has the highest priority and level 3 has
the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces
The 8031 and compatible family of microcon-
trollers, which includes the 80C51, 80C151,
80C251, 80C51XA, and the C500 family, have
separate address spaces for code memory (se-
lected using PSEN) and data memory (selected
Highest Priority
Lowest Priority
0 = PSEN
can’t access
Flash
memory
1 = PSEN
access
Flash
memory
FL_Code
Bit 2
EEPROM Memory
0 = PSEN can’t
access EEPROM
1 = PSEN
access EEPROM
SRAM, I /O, or
Peripheral I /O
Flash Memory
Secondary
EE_Code
Level 1
Level 2
Level 3
Bit 1
PSD813F1A
0 = PSEN
can’t access
SRAM
1 = PSEN
access
SRAM
SRAM_Code
Bit 0
AI09221
31/111
12