PSD813F1A-90MI STMicroelectronics, PSD813F1A-90MI Datasheet - Page 34

• Manufacturer Part Number: PSD813F1A-90MI
• Description: IC FLASH 1MBIT 90NS 52QFP
• Manufacturer: STMicroelectronics

Specifications of PSD813F1A-90MI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1978

PSD813F1A
PLD’S
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using the PSDabel tool in PSDsoft Express, the
logic is programmed into the device and available
upon power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the sections entitled
CODE PLD (DPLD)
Figure 15., page 35
PLDs.
The DPLD performs address decoding for internal
and external components, such as memory, regis-
ters, and I/O port selects.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output macrocells (OMCs), 24 Input macrocells
(IMCs), and the AND array. The CPLD can also be
used to generate external chip selects.
The AND array is used to form product terms.
These product terms are specified using PSDabel.
An Input Bus consisting of 73 signals is connected
to the PLDs. The signals are shown in Table 13.
The Turbo Bit in PSD
The PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns.
Setting the Turbo mode bit to off (Bit 3 of the
PMMR0 register) automatically places the PLDs
into standby if no inputs are changing. Turbo-off
mode increases propagation delays while reduc-
ing power consumption. See the section entitled
POWER MANAGEMENT, page
the Turbo Bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
34/111
shows the configuration of the
and
COMPLEX PLD
64, on how to set
(CPLD).
DE-
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
The PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns. Each
of the two PLDs has unique characteristics suited
for its applications. They are described in the fol-
lowing sections.
Table 13. DPLD and CPLD Inputs
MCU Address Bus
MCU Control Signals
Reset
Power-down
Port A Input
Macrocells
Port B Input
Macrocells
Port C Input
Macrocells
Port D Inputs
Page Register
Macrocell AB
Feedback
Macrocell BC
Feedback
EEPROM Program
Status Bit
Input Source
1
A15-A0
CNTL2-CNTL0
RST
PDN
PA7-PA0
PB7-PB0
PC7-PC0
PD2-PD0
PGR7-PGR0
MCELLAB.FB7-
FB0
MCELLBC.FB7-
FB0
Ready/Busy
Input Name
Number
Signals
16
of
3
1
1
8
8
8
3
8
8
8
1