PSD813F1A-90MI STMicroelectronics, PSD813F1A-90MI Datasheet - Page 59

IC FLASH 1MBIT 90NS 52QFP

PSD813F1A-90MI

Manufacturer Part Number
PSD813F1A-90MI
Description
IC FLASH 1MBIT 90NS 52QFP
Manufacturer
STMicroelectronics
Datasheet

Specifications of PSD813F1A-90MI

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
1M (128K x 8)
Speed
90ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
52-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1978

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PSD813F1A-90MI
Manufacturer:
STMicroelectronics
Quantity:
10 000
Port Data Registers
The Port Data Registers, shown in Table 27, are
used by the MCU to write data to or read data from
the ports. Table
ports having each register type, and MCU access
for each register type. The registers are described
below.
Data In
Port pins are connected directly to the Data In buf-
fer. In MCU I/O input mode, the pin input is read
through the Data In buffer.
Data Out Register
Stores output data written by the MCU in the MCU
I/O output mode. The contents of the Register are
driven out to the pins if the Direction Register or
the output enable product term is set to ‘1.’ The
contents of the register can also be read back by
the MCU.
Table 27. Port Data Registers
Data In
Data Out
Output Macrocell
Mask Macrocell
Input Macrocell
Enable Out
Register Name
27
shows the register name, the
A,B,C,D
A,B,C,D
A,B,C
A,B,C
A,B,C
A,B,C
Port
READ – input on pin
WRITE/READ
READ – outputs of macrocells
WRITE – loading macrocell flip-flop
WRITE/READ – prevents loading into a given
macrocell
READ – outputs of the Input Macrocells
READ – the output enable control of the port driver
Output Macrocells (OMC)
The CPLD Output Macrocells (OMC) occupy a lo-
cation in the microcontroller’s address space. The
microcontroller can read the output of the OMCs.
If the Mask Macrocell Register bits are not set,
writing to the Macrocell loads data to the Macrocell
flip flops. See the section entitled
Mask Macrocell Register
Each Mask Register bit corresponds to an OMC
flip flop. When the Mask Register bit is set to a “1”,
loading data into the OMC flip flop is blocked. The
default value is “0” or unblocked.
Input Macrocells (IMC)
The IMCs can be used to latch or store external in-
puts. The outputs of the IMCs are routed to the
PLD input bus, and can be read by the microcon-
troller.
PLD’S, page 34
Refer
MCU Access
for a detailed description.
to
the
section
PLD’S, page
PSD813F1A
entitled
59/111
34.

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