DP8421AV-25 National Semiconductor, DP8421AV-25 Datasheet - Page 20

IC CTRLR/DVR CMOS PROGRAM 68PLCC

DP8421AV-25

Manufacturer Part Number
DP8421AV-25
Description
IC CTRLR/DVR CMOS PROGRAM 68PLCC
Manufacturer
National Semiconductor
Datasheet

Specifications of DP8421AV-25

Controller Type
Dynamic RAM (DRAM)
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP8421AV-25

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4 0 Port A Access Modes
4 5 3 Delay CAS during Write Accesses
Address bit C9 asserted during programming will cause CAS
to be delayed until the first positive edge of CLK after RAS
is asserted when the input WIN is asserted Delaying CAS
during write accesses ensures that the data to be written to
DRAM will be setup to CAS asserting as shown in Figures
(Continued)
FIGURE 12b Mode 1 Delay CAS
FIGURE 12a Mode 0 Delay CAS
20
12a and 12b If the possibility exists that data still may not
be present after the first positive edge of CLK CAS can be
delayed further with the ECAS inputs If address bit C9 is
negated during programming read and write accesses will
be treated the same (with regard to CAS)
TL F 8588 – C7
TL F 8588 – C8

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